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DATA SHEET
PD780021A, 780022A, 780023A, 780024A 780021AY, 780022AY, 780023AY, 780024AY
8-BIT SINGLE-CHIP MICROCONTROLLERS
MOS INTEGRATED CIRCUIT
DESCRIPTION
The PD780021A, 780022A, 780023A, and 780024A are members of the PD780024A Subseries of the 78K/0 Series. Only selected functions of the existing PD78054 Subseries are provided, and the serial interface is enhanced. The PD780021AY, 780022AY, 780023AY, and 780024AY are the PD780024A Subseries with a multimaster supporting I2C bus interface, which makes them suitable for AV equipment. Flash memory versions, the PD78F0034A, 78F0034B, 78F0034AY, and 78F0034BY, that can operate in the same power supply voltage range as the mask ROM versions, and various development tools, are also available. Detailed function descriptions are provided in the following user's manuals. Be sure to read them before designing. PD780024A, 780034A, 780024AY, 780034AY Subseries User's Manual: U14046E 78K/0 Series Instructions User's Manual: U12326E
FEATURES
* Internal ROM and RAM
Item Part Number Program Memory (Internal ROM) 8 KB 16 KB 24 KB 32 KB 1024 bytes Data Memory (Internal High-Speed RAM) 512 bytes Package * 64-pin plastic SDIP (19.05 mm (750)) * 64-pin plastic QFP (14 x 14) * 64-pin plastic LQFP (14 x 14) * 64-pin plastic TQFP (12 x 12) * 64-pin plastic LQFP (10 x 10) * 73-pin plastic FBGA (9 x 9)
PD780021A, 780021AY PD780022A, 780022AY PD780023A, 780023AY PD780024A, 780024AY
* External memory expansion space: 64 KB * Minimum instruction execution time * Expanded-specification products of PD780021A, 780022A, 780023A, 780024A: 0.166 s (fX = 12 MHz, VDD = 4.5 to 5.5 V) * PD780021AY, 780022AY, 780023AY, 780024AY and conventional products of PD780021A, 780022A, 780023A, 780024A: 0.238 s (fX = 8.38 MHz, VDD = 4.0 to 5.5 V) * I/O ports: 51 (N-ch open-drain (5 V withstanding voltage): 4) * 8-bit resolution A/D converter: 8 channels (AVDD = 1.8 to 5.5 V) * Serial interface: 3 channels * PD780021A, 780022A, 780023A, 780024A: UART mode, 3-wire serial I/O mode (2 channels) * PD780021AY, 780022AY, 780023AY, 780024AY: UART mode, 3-wire serial I/O mode, I2C bus mode * Timer: 5 channels * Power supply voltage: VDD = 1.8 to 5.5 V
The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information.
Document No. U14042EJ4V0DS00 (4th edition) Date Published December 2002 N CP(K) Printed in Japan
The mark
shows major revised points.
(c)
(c)
2000
PD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
APPLICATIONS
Telephones, household electrical appliances, pagers, AV equipment, car audios, office automation equipment, etc.
ORDERING INFORMATION (1/2)
(1) PD780024A Subseries Part Number Package 64-pin plastic SDIP (19.05 mm (750)) 64-pin plastic QFP (14 x 14) 64-pin plastic LQFP (14 x 14) 64-pin plastic TQFP (12 x 12) 64-pin plastic LQFP (10 x 10) 73-pin plastic FBGA (9 x 9) 64-pin plastic SDIP (19.05 mm (750)) 64-pin plastic QFP (14 x 14) 64-pin plastic LQFP (14 x 14) 64-pin plastic TQFP (12 x 12) 64-pin plastic LQFP (10 x 10) 73-pin plastic FBGA (9 x 9) 64-pin plastic SDIP (19.05 mm (750)) 64-pin plastic QFP (14 x 14) 64-pin plastic LQFP (14 x 14) 64-pin plastic TQFP (12 x 12) 64-pin plastic LQFP (10 x 10) 73-pin plastic FBGA (9 x 9) 64-pin plastic SDIP (19.05 mm (750)) 64-pin plastic QFP (14 x 14) 64-pin plastic LQFP (14 x 14) 64-pin plastic TQFP (12 x 12) 64-pin plastic LQFP (10 x 10) 73-pin plastic FBGA (9 x 9)
PD780021ACW-xxx PD780021AGC-xxx-AB8 PD780021AGC-xxx-8BS PD780021AGK-xxx-9ET PD780021AGB-xxx-8EU PD780021AF1-xxx-CN3 PD780022ACW-xxx PD780022AGC-xxx-AB8 PD780022AGC-xxx-8BS PD780022AGK-xxx-9ET PD780022AGB-xxx-8EU PD780022AF1-xxx-CN3 PD780023ACW-xxx PD780023AGC-xxx-AB8 PD780023AGC-xxx-8BS PD780023AGK-xxx-9ET PD780023AGB-xxx-8EU PD780023AF1-xxx-CN3 PD780024ACW-xxx PD780024AGC-xxx-AB8 PD780024AGC-xxx-8BS PD780024AGK-xxx-9ET PD780024AGB-xxx-8EU PD780024AF1-xxx-CN3
Remark xxx indicates ROM code suffix.
2
Data Sheet U14042EJ4V0DS
PD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
ORDERING INFORMATION (2/2)
(2) PD780024AY Subseries Part Number Package 64-pin plastic SDIP (19.05 mm (750)) 64-pin plastic QFP (14 x 14) 64-pin plastic LQFP (14 x 14) 64-pin plastic TQFP (12 x 12) 64-pin plastic LQFP (10 x 10) 73-pin plastic FBGA (9 x 9) 64-pin plastic SDIP (19.05 mm (750)) 64-pin plastic QFP (14 x 14) 64-pin plastic LQFP (14 x 14) 64-pin plastic TQFP (12 x 12) 64-pin plastic LQFP (10 x 10) 73-pin plastic FBGA (9 x 9) 64-pin plastic SDIP (19.05 mm (750)) 64-pin plastic QFP (14 x 14) 64-pin plastic LQFP (14 x 14) 64-pin plastic TQFP (12 x 12) 64-pin plastic LQFP (10 x 10) 73-pin plastic FBGA (9 x 9) 64-pin plastic SDIP (19.05 mm (750)) 64-pin plastic QFP (14 x 14) 64-pin plastic LQFP (14 x 14) 64-pin plastic TQFP (12 x 12) 64-pin plastic LQFP (10 x 10) 73-pin plastic FBGA (9 x 9)
PD780021AYCW-xxx PD780021AYGC-xxx-AB8 PD780021AYGC-xxx-8BS PD780021AYGK-xxx-9ET PD780021AYGB-xxx-8EU PD780021AYF1-xxx-CN3 PD780022AYCW-xxx PD780022AYGC-xxx-AB8 PD780022AYGC-xxx-8BS PD780022AYGK-xxx-9ET PD780022AYGB-xxx-8EU PD780022AYF1-xxx-CN3 PD780023AYCW-xxx PD780023AYGC-xxx-AB8 PD780023AYGC-xxx-8BS PD780023AYGK-xxx-9ET PD780023AYGB-xxx-8EU PD780023AYF1-xxx-CN3 PD780024AYCW-xxx PD780024AYGC-xxx-AB8 PD780024AYGC-xxx-8BS PD780024AYGK-xxx-9ET PD780024AYGB-xxx-8EU PD780024AYF1-xxx-CN3
Remark xxx indicates ROM code suffix.
Data Sheet U14042EJ4V0DS
3
PD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
EXPANDED-SPECIFICATION PRODUCTS AND CONVENTIONAL PRODUCTS
The expanded-specification product and conventional product refer to the following products. Expanded-specification product: PD780021A, 780022A, 780023A, 780024A for which orders were received after December 1, 2001. (Products with a rankNote other than K, E, P, X) Conventional product: Products other than the above expanded specification products. (Products with rankNote K, E, P, X)
PD780021AY, 780022AY, 780023AY, 780024AY
Note The rank is indicated by the 5th digit from the left in the lot number marked on the package.
Lot number
Year code Week code NEC Electronics control code Rank
Expanded-specification products and conventional products differ in the power supply voltage range and operating frequency ratings.
Power Supply Voltage (VDD) Guaranteed Operating Speed (Operating Frequency) Conventional Products 4.5 to 5.5 V 4.0 to 5.5 V 3.0 to 5.5 V 2.7 to 5.5 V 1.8 to 5.5 V 8.38 MHz (0.238 s) 8.38 MHz (0.238 s) 5 MHz (0.4 s) 5 MHz (0.4 s) 1.25 MHz (1.6 s) Expanded-Specification Products 12 MHz (0.166 s) 8.38 MHz (0.238 s) 8.38 MHz (0.238 s) 5 MHz (0.4 s) 1.25 MHz (1.6 s)
Remark The parenthesized values indicates the minimum instruction execution time.
CORRESPONDENCE BETWEEN MASK ROM PRODUCTS AND FLASH MEMORY PRODUCTS
Mask ROM Products Expanded-specification products of PD780021A, 780022A, 780023A, 780024A Conventional products of PD780021A, 780022A, 780023A, 780024A Flash Memory Products
PD78F0034B PD78F0034A PD78F0034AY, 78F0034BY
PD780021AY, 780022AY, 780023AY, 780024AY
Remark
The PD78F0034A and 78F0034B differ in the operating frequency ratings and communication mode of flash memory programming. The PD78F0034AY and 78F0034BY only differ in the communication mode of flash memory programming. Refer to the data sheet of the products.
4
Data Sheet U14042EJ4V0DS
PD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
78K/0 SERIES LINEUP
The products in the 78K/0 Series are listed below. The names enclosed in boxes are subseries names.
Products in mass production Products under development
Y subseries products are compatible with I2C bus. Control 100-pin 100-pin 100-pin 100-pin 80-pin 80-pin 80-pin 80-pin 64-pin 64-pin 64-pin 52-pin 52-pin 64-pin 64-pin 42/44-pin
PD78075B PD78078 PD78070A PD780058 PD78058F PD78054 PD780065 PD780078 PD780034A PD780024A PD780034AS
PD780024AS PD78014H
EMI-noise reduced version of the PD78078
PD78078Y PD78070AY PD780018AY PD780058Y PD78058FY PD78054Y
PD78054 with timer and enhanced external interface
ROMless version of the PD78078 PD78078Y with enhanced serial I/O and limited function
PD78054 with enhanced serial I/O
EMI-noise reduced version of the PD78054
PD78018F with UART and D/A converter, and enhanced I/O PD780024A with expanded RAM PD780034A with timer and enhanced serial I/O PD780078Y PD780034AY PD780024A with enhanced A/D converter PD780024AY PD78018F with enhanced serial I/O 52-pin version of the PD780034A
52-pin version of the PD780024A EMI-noise reduced version of the PD78018F
PD78018F PD78083
Inverter control
PD78018FY
Basic subseries for control On-chip UART, capable of operating at low voltage (1.8 V)
64-pin
PD780988
VFD drive
On-chip inverter control circuit and UART. EMI-noise reduced.
100-pin 80-pin 80-pin 80-pin
PD780208 PD780232 PD78044H PD78044F
LCD drive
PD78044F with enhanced I/O and VFD C/D. Display output total: 53
For panel control. On-chip VFD C/D. Display output total: 53
PD78044F with N-ch open-drain I/O. Display output total: 34
Basic subseries for driving VFD. Display output total: 34
78K/0 Series
100-pin 100-pin 120-pin 120-pin 120-pin 100-pin 100-pin 100-pin
PD780354 PD780344 PD780338 PD780328 PD780318 PD780308 PD78064B PD78064
PD780354Y PD780344Y
PD780344 with enhanced A/D converter PD780308 with enhanced display function and timer. PD780308 with enhanced display function and timer. PD780308 with enhanced display function and timer. PD780308 with enhanced display function and timer.
Segment signal output: 40 pins max. Segment signal output: 40 pins max. Segment signal output: 32 pins max. Segment signal output: 24 pins max.
PD780308Y PD78064Y
PD78064 with enhanced SIO, and expanded ROM and RAM EMI-noise reduced version of the PD78064
Basic subseries for driving LCDs, on-chip UART
Bus interface supported 100-pin 80-pin 80-pin 80-pin 80-pin 64-pin
PD780948 PD78098B PD780702Y PD780703Y PD780833Y
PD780816
Meter control
On-chip CAN controller
PD78054 with IEBusTM controller
On-chip IEBus controller On-chip CAN controller On-chip controller compliant with J1850 (Class 2) Specialized for CAN controller function
100-pin 80-pin 80-pin
PD780958 PD780852 PD780828B
For industrial meter control On-chip automobile meter controller/driver For automobile meter driver. On-chip CAN controller
Remark VFD (Vacuum Fluorescent Display) is referred to as FIPTM (Fluorescent Indicator Panel) in some documents, but the functions of the two are same.
Data Sheet U14042EJ4V0DS
5
PD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
The major functional differences among the subseries are listed below. * Non-Y subseries
Function Subseries Name Control ROM Timer 8-Bit 10-Bit 8-Bit Capacity (Bytes) 8-Bit 16-Bit Watch WDT A/D A/D D/A 1 ch 1 ch 1 ch 8 ch - Serial Interface I/O VDD External MIN. Value Expansion 1.8 V
PD78075B 32 K to 40 K 4 ch PD78078 PD78070A
48 K to 60 K -
2 ch 3 ch (UART: 1 ch)
88
61 3 ch (time-division UART: 1 ch) 3 ch (UART: 1 ch) 68 69
2.7 V 1.8 V 2.7 V 2.0 V
PD780058 24 K to 60 K 2 ch PD78058F 48 K to 60 K PD78054
16 K to 60 K - 2 ch 1 ch 8 ch - 4 ch 8 ch - 4 ch - - 8 ch
PD780065 40 K to 48 K PD780078 48 K to 60 K
PD780034A 8 K to 32 K PD780024A
PD780034AS PD780024AS
4 ch (UART: 1 ch) 3 ch (UART: 2 ch) 3 ch (UART: 1 ch)
60 52 51
2.7 V 1.8 V
39
-
PD78014H PD78018F 8 K to 60 K PD78083
Inverter control VFD drive 8 K to 16 K - - - 1 ch
2 ch
53
1 ch (UART: 1 ch) - 8 ch - 3 ch (UART: 2 ch)
33 47 4.0 V
- -
PD780988 16 K to 60 K 3 ch Note PD780208 32 K to 60 K 2 ch PD780232 16 K to 24 K 3 ch PD78044H 32 K to 48 K 2 ch PD78044F 16 K to 40 K
1 ch - 1 ch
1 ch - 1 ch
1 ch
8 ch 4 ch 8 ch
-
-
2 ch
74 40
2.7 V 4.5 V 2.7 V
1 ch 2 ch
68
LCD drive
PD780354 24 K to 32 K 4 ch PD780344 PD780338 48 K to 60 K 3 ch PD780328 PD780318 PD780308 48 K to 60 K 2 ch PD78064B 32 K PD78064
16 K to 32 K 2 ch
1 ch
1 ch
1 ch
- 8 ch
8 ch -
-
3 ch (UART: 1 ch)
66
1.8 V
-
2 ch
-
10 ch 1 ch 2 ch (UART: 1 ch)
54 62 70
1 ch
8 ch
-
-
3 ch (time-division UART: 1 ch) 2 ch (UART: 1 ch)
57
2.0 V
Bus interface
PD780948 60 K PD78098B 40 K to 60 K
2 ch 1 ch 2 ch 2 ch
1 ch
1 ch
8 ch
-
- 2 ch
3 ch (UART: 1 ch)
79 69
4.0 V 2.7 V 4.0 V 2.2 V
-
supported PD780816 32 K to 60 K Meter control Dashboard control
12 ch - 1 ch - -
- -
2 ch (UART: 1 ch) 2 ch (UART: 1 ch)
46 69
PD780958 48 K to 60 K 4 ch PD780852 32 K to 40 K 3 ch
PD780828B 32 K to 60 K
-
1 ch
1 ch
1 ch
5 ch
-
-
3 ch (UART: 1 ch)
56 59
4.0 V
-
Note 16-bit timer: 2 channels 10-bit timer: 1 channel
6
Data Sheet U14042EJ4V0DS
PD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
* Y subseries
Function Subseries Name Control ROM Capacity (Bytes) Timer 8-Bit 10-Bit 8-Bit A/D - D/A 2 ch 3 ch (UART: 1 ch, I2C: 1 ch) 88 61 - 3 ch (I C: 1 ch)
2 2
Serial Interface
I/O
8-Bit 16-Bit Watch WDT A/D 1 ch 1 ch 1 ch 8 ch
VDD External MIN. Value Expansion 1.8 V 2.7 V
PD78078Y 48 K to 60 K 4 ch
PD78070AY
-
PD780018AY 48 K to 60 K
88 68 69 1.8 V 2.7 V 2.0 V
PD780058Y 24 K to 60 K 2 ch
PD78058FY 48 K to 60 K
2 ch 3 ch (time-division UART: 1 ch, I C: 1 ch) 3 ch (UART: 1 ch, I C: 1 ch)
2
PD78054Y 16 K to 60 K
PD780078Y 48 K to 60 K
PD780034AY 8 K to 32 K PD780024AY
2 ch 1 ch 8 ch - 2 ch (I2C: 1 ch) 1 ch 1 ch 1 ch - 8 ch 8 ch - - 4 ch (UART: 1 ch, I2C: 1 ch) 3 ch (time-division UART: 1 ch, I2C: 1 ch) 2 ch (UART: 1 ch, I C: 1 ch) 3 ch 2 ch 1 ch 1 ch 16 ch - - 4 ch (UART: 1 ch, I2C: 1 ch) 67
2
-
8 ch
-
4 ch (UART: 2 ch, I C: 1 ch)
2
2
52
1.8 V
3 ch (UART: 1 ch, I C: 1 ch) 51
PD78018FY 8 K to 60 K
LCD drive
53 66 1.8 V -
PD780354Y 24 K to 32 K 4 ch PD780344Y PD780308Y 48 K to 60 K 2 ch
57
2.0 V
PD78064Y 16 K to 32 K
Bus PD780701Y 60 K interface PD780703Y supported PD780833Y
3.5 V
-
65
4.5 V
Remark
The functions of non-Y subseries and Y subseries products are the same, except for the serial interface.
Data Sheet U14042EJ4V0DS
7
PD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
OVERVIEW OF FUNCTIONS (1/2)
Part Number Item Internal memory Memory space General-purpose registers Minimum instruction execution time ROM High-speed RAM
PD780021A PD780021AY
8 KB 512 bytes 64 KB
PD780022A PD780022AY
16 KB
PD780023A PD780023AY
24 KB 1024 bytes
PD780024A PD780024AY
32 KB
8 bits x 32 registers (8 bits x 8 registers x 4 banks) On-chip minimum instruction execution time cycle variable function
When main system * Expanded-specification products of PD780021A, 780022A, 780023A, 780024A: clock selected 0.166 s/0.333 s/0.666 s/1.33 s/2.66 s (@12 MHz, VDD = 4.5 to 5.5 V operation) * PD780021AY, 780022AY, 780023AY, 780024AY and conventional products of PD780021A, 780022A, 780023A, 780024A: 0.238 s/0.48 s/0.95 s/1.91 s/3.81 s (@8.38 MHz, VDD = 4.0 to 5.5 V operation) When subsystem clock selected 122 s (@ 32.768 kHz operation) * 16-bit operation * Multiply/divide (8 bits x 8 bits,16 bits / 8 bits) * Bit manipulation (set, reset, test, Boolean operation) * BCD adjust, etc.
Instruction set
I/O ports
Total:
51
* CMOS input: 8 * CMOS I/O: 39 * N-ch open-drain I/O (5 V withstanding voltage): 4 A/D converter * 8-bit resolution x 8 channels * Low-voltage operation available: AVDD = 1.8 to 5.5 V Serial interface * PD780021A, 780022A, 780023A, 780024A UART mode: 1 channel 3-wire serial I/O mode: 2 channels * PD780021AY, 780022AY, 780023AY, 780024AY UART mode: 1 channel 3-wire serial I/O mode: 1 channel I2C bus mode (multimaster supporting): 1 channel * * * * 16-bit timer/event counter: 8-bit timer/event counter: Watch timer: Watchdog timer: 1 2 1 1 channel channels channel channel
Timers
Timer outputs
3 (8-bit PWM output capable: 2)
8
Data Sheet U14042EJ4V0DS
PD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
OVERVIEW OF FUNCTIONS (2/2)
Part Number Item Clock output
PD780021A PD780021AY
PD780022A PD780022AY
PD780023A PD780023AY
PD780024A PD780024AY
* Expanded-specification products of PD780021A, 780022A, 780023A, 780024A: 93.75 kHz, 187.5 kHz, 375 kHz, 750 kHz, 1.25 MHz, 3 MHz, 6 MHz, 12 MHz (@12MHz operation with main system clock) 32.768 kHz (@ 32.768 kHz operation with subsystem clock) * PD780021AY, 780022AY, 780023AY, 780024AY and conventional products of PD780021A, 780022A, 780023A, 780024A: 65.5 kHz, 131 kHz, 262 kHz, 524 kHz, 1.05 MHz, 2.10 MHz, 4.19 MHz, 8.38 MHz (@ 8.38 MHz operation with main system clock) 32.768 kHz (@ 32.768 kHz operation with subsystem clock) * Expanded-specification products of PD780021A, 780022A, 780023A, 780024A: 1.46 kHz, 2.93 kHz, 5.86 kHz, 11.7 kHz (@ 12 MHz operation with main system clock) * PD780021AY, 780022AY, 780023AY, 780024AY and conventional products of PD780021A, 780022A, 780023A, 780024A: 1.02 kHz, 2.05 kHz, 4.10 kHz, 8.19 kHz (@ 8.38 MHz operation with main system clock) Maskable Non-maskable Software Internal: 13, external: 5 Internal: 1 1 VDD = 1.8 to 5.5 V TA = -40 to +85C * 64-pin plastic SDIP (19.05 mm (750)) * 64-pin plastic QFP (14 x 14) * 64-pin plastic LQFP (14 x 14) * 64-pin plastic TQFP (12 x 12) * 64-pin plastic LQFP (10 x 10) * 73-pin plastic FBGA (9 x 9)
Buzzer output
Vectored interrupt sources
Power supply voltage Operating ambient temperature Package
Data Sheet U14042EJ4V0DS
9
PD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
CONTENTS
1. PIN CONFIGURATION (TOP VIEW) ................................................................................................. 11 2. BLOCK DIAGRAM .............................................................................................................................15 3. PIN FUNCTIONS ................................................................................................................................16
3.1 3.2 3.3 Port Pins .................................................................................................................................................... 16 Non-Port Pins ............................................................................................................................................ 17 Pin I/O Circuits and Recommended Connection of Unused Pins ..................................................... 19
4. MEMORY SPACE ...............................................................................................................................21 5. PERIPHERAL HARDWARE FUNCTION FEATURES...................................................................... 22
5.1 5.2 5.3 5.4 5.5 5.6 Ports ........................................................................................................................................................... 22 Clock Generator ........................................................................................................................................ 23 Timer/Counter ........................................................................................................................................... 24 Clock Output/Buzzer Output Controller ................................................................................................ 28 A/D Converter ........................................................................................................................................... 29 Serial Interface .......................................................................................................................................... 30
6. INTERRUPT FUNCTIONS .................................................................................................................33 7. EXTERNAL DEVICE EXPANSION FUNCTION ...............................................................................36 8. STANDBY FUNCTION .......................................................................................................................36 9. RESET FUNCTION ............................................................................................................................36 10. MASK OPTION ...................................................................................................................................36 11. INSTRUCTION SET ...........................................................................................................................37 12. ELECTRICAL SPECIFICATIONS ......................................................................................................39
12.1 Expanded-Specification Products of PD780021A, 780022A, 780023A, 780024A .......................... 39 12.2 PD780021AY, 780022AY, 780023AY, 780024AY, and Conventional Products of PD780021A, 780022A, 780023A, 780024A .................................................................................................................................... 55 12.3 Timing Chart .............................................................................................................................................. 71
13. PACKAGE DRAWINGS .....................................................................................................................77 14. RECOMMENDED SOLDERING CONDITIONS ................................................................................83 APPENDIX A. DEVELOPMENT TOOLS ................................................................................................87 APPENDIX B. RELATED DOCUMENTS ...............................................................................................91
10
Data Sheet U14042EJ4V0DS
PD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
1. PIN CONFIGURATION (TOP VIEW)
* 64-pin plastic SDIP (19.05 mm (750))
P40/AD0 P41/AD1 P42/AD2 P43/AD3 P44/AD4 P45/AD5 P46/AD6 P47/AD7 P50/A8 P51/A9 P52/A10 P53/A11 P54/A12 P55/A13 P56/A14 P57/A15 VSS0 VDD0 P30 P31 P32/SDA0Note 1 P33/SCL0Note 1 P34/SI31Note 2 P35/SO31Note 2 P36/SCK31Note 2 P20/SI30 P21/SO30 P22/SCK30 P23/RxD0 P24/TxD0 P25/ASCK0 VDD1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
P67/ASTB P66/WAIT P65/WR P64/RD P75/BUZ P74/PCL P73/TI51/TO51 P72/TI50/TO50 P71/TI01 P70/TI00/TO0 P03/INTP3/ADTRG P02/INTP2 P01/INTP1 P00/INTP0 VSS1 X1 X2 IC XT1 XT2 RESET AVDD AVREF P10/ANI0 P11/ANI1 P12/ANI2 P13/ANI3 P14/ANI4 P15/ANI5 P16/ANI6 P17/ANI7 AVSS
Notes 1. SDA0 and SCL0 are incorporated only in the PD780024AY Subseries. 2. SI31, SO31, and SCK31 are incorporated only in the PD780024A Subseries. Cautions 1. Connect the IC (Internally Connected) pin directly to VSS0 or VSS1. 2. Connect the AVSS pin to VSS0. Remark When the PD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, and 780024AY are used in applications where the noise generated inside the microcontroller needs to be reduced, the implementation of noise reduction measures, such as supplying voltage to VDD0 and VDD1 individually and connecting VSS0 and VSS1 to different ground lines, is recommended.
Data Sheet U14042EJ4V0DS
11
PD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
* 64-pin plastic QFP (14 x 14) * 64-pin plastic LQFP (14 x 14) * 64-pin plastic TQFP (12 x 12) * 64-Pin plastic LQFP (10 x 10)
P73/TI51/TO51 P72/TI50/TO50
P67/ASTB
P66/WAIT
P75/BUZ
P47/AD7
P46/AD6
P45/AD5
P44/AD4
P43/AD3
P42/AD2
P41/AD1
P40/AD0
P50/A8 P51/A9 P52/A10 P53/A11 P54/A12 P55/A13 P56/A14 P57/A15 VSS0 VDD0 P30 P31 P32/SDA0Note 1 P33/SCL0Note 1 P34/SI31Note 2 P35/SO31
Note 2
1 2 3 4 5 6 7 8 9
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34
P74/PCL
P65/WR
P64/RD
P71/TI01 P70/TI00/TO0 P03/INTP3/ADTRG P02/INTP2 P01/INTP1 P00/INTP0 VSS1 X1 X2 IC XT1 XT2 RESET AVDD AVREF P10/ANI0
10 11 12 13 14 15
16 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
P36/SCK31Note 2
P21/SO30
P23/RxD0
P20/SI30
P22/SCK30
P24/TxD0
P25/ASCK0
AVSS
VDD1
P17/ANI7
P16/ANI6
P15/ANI5
P14/ANI4
P13/ANI3
P12/ANI2
Notes 1. SDA0 and SCL0 are incorporated only in the PD780024AY Subseries. 2. SI31, SO31, and SCK31 are incorporated only in the PD780024A Subseries. Cautions 1. Connect the IC (Internally Connected) pin directory to VSS0 or VSS1. 2. Connect the AVSS pin to VSS0. Remark When the PD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, and 780024AY are used in applications where the noise generated inside the microcontroller needs to be reduced, the implementation of noise reduction measures, such as supplying voltage to VDD0 and VDD1 individually and connecting VSS0 and VSS1 to different ground lines, is recommended.
12
Data Sheet U14042EJ4V0DS
P11/ANI1
PD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
* 73-pin plastic FBGA (9 x 9)
Top View 9 8 7 6 5 4 3 2 1 ABCDEFGHJ JHGFEDCBA Bottom View
Index mark
Pin No. A1 A2 A3 A4 A5 A6 A7 A8 A9 B1 B2 B3 B4 B5 B6 B7 B8 B9 Pin Name NC P46/AD6 P44/AD4 P41/AD1 P67/ASTB P65/WR P74/PCL NC NC P51/A9 P47/AD7 P43/AD3 P40/AD0 P66/WAIT P75/BUZ P72/TI50/TO51 P71/TI01 P70/TI00/TO0 Pin No. C1 C2 C3 C4 C5 C6 C7 C8 C9 D1 D2 D3 D4 D5 D6 D7 D8 D9 Pin Name P52/A10 P53/A11 P45/AD5 P42/AD2 P64/RD P73/TI51/TO51 P03/INTP3/ADTRG P01/INTP1 VSS1 P55/A13 P56/A14 P50/A8 NC - - P02/INTP2 IC X1 Pin No. E1 E2 E3 E4 E5 E6 E7 E8 E9 F1 F2 F3 F4 F5 F6 F7 F8 F9 Pin Name P57/A15 VDD0 P54/A12 - - - P00/INTP0 XT1 X2 P30 P31 VSS0 - - - P14/ANI4 RESET XT2 Pin No. G1 G2 G3 G4 G5 G6 G7 G8 G9 H1 H2 H3 H4 H5 H6 H7 H8 H9 Pin Name P33/SCL0Note 1 P32/SDA0Note 1 P20/SI30 P21/SO30 P24/TxD0 VDD1 P16/ANI6 AVDD NC P34/SI31Note 2 P35/SO31Note 2 P23/RxD0 P22/SCK30 AVSS P15/ANI5 P11/ANI1 P10/ANI0 AVREF Pin No. J1 J2 J3 J4 J5 J6 J7 J8 J9 Pin Name NC P36/SCK31Note 2 NC P25/ASCK0 NC P17/ANI7 P12/ANI2 P13/ANI3 NC
Notes 1. SDA0 and SCL0 are incorporated only in the PD780024AY Subseries. 2. SI31, SO31, and SCK31 are incorporated only in the PD780024A Subseries. Cautions 1. Connect the IC (Internally Connected) pin directory to VSS0 or VSS1. 2. Connect the AVSS pin to VSS0. Remark When the PD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, and 780024AY are used in applications where the noise generated inside the microcontroller needs to be reduced, the implementation of noise reduction measures, such as supplying voltage to VDD0 and VDD1 individually and connecting VSS0 and VSS1 to different ground lines, is recommended.
Data Sheet U14042EJ4V0DS
13
PD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
A8 to A15: AD0 to AD7: ADTRG: ANI0 to ANI7: ASCK0: ASTB: AVDD: AVREF: AVSS: BUZ: IC: INTP0 to INTP3: NC: P00 to P03: P10 to P17: P20 to P25: P30 to P36: P40 to P47: P50 to P57: Address bus Address/data bus AD trigger input Analog input Asynchronous serial clock Address strobe Analog power supply Analog reference voltage Analog ground Buzzer clock Internally connected External interrupt input No connection Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 P64 to P67: P70 to P75: PCL: RD: RESET: RxD0: SDA0: SI30, SI31: SO30, SO31: TO0, TO50, TO51: TxD0: VDD0, VDD1: VSS0, VSS1: WAIT: WR: X1, X2: XT1, XT2: Port 6 Port 7 Programmable clock Read strobe Reset Receive data Serial data Serial input Serial output Timer output Transmit data Power supply Ground Wait Write strobe Crystal (main system clock) Crystal (subsystem clock)
SCK30, SCK31, SCL0: Serial clock
TI00, TI01, TI50, TI51: Timer input
14
Data Sheet U14042EJ4V0DS
PD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
2. BLOCK DIAGRAM
TI00/TO0/P70 TI01/P71 TI50/TO50/P72 TI51/TO51/P73 16-bit timer/ event counter 8-bit timer/ event counter 50 8-bit timer/ event counter 51 Watchdog timer Watch timer SI30/P20 SO30/P21 SCK30/P22 SI31/P34 SO31/P35 SCK31/P36 RxD0/P23 TxD0/P24 ASCK0/P25 SDA0/P32 SCL0/P33 ANI0/P10 to ANI7/P17 AVDD AVSS AVREF INTP0/P00 to INTP3/P03 BUZ/P75 PCL/P74 Port 0 P00 to P03
Port 1
P10 to P17
Port 2
P20 to P25
Port 3
P30 to P36
78K/0 CPU core
ROM
Port 4
P40 to P47
Serial interface 30
Port 5
P50 to P57
Port 6 Serial interface 31Note 1 RAM UART0
P64 to P67
Port 7
P70 to P75
AD0/P40 to AD7/P47 A8/P50 to A15/P57 External access RD/P64 WR/P65 WAIT/P66 ASTB/P67
I2C busNote 2
A/D converter RESET X1 X2 XT1 XT2
Interrupt control Buzzer output Clock output control
System control
VDD0 VDD1 VSS0 VSS1
IC
Notes 1. Incorporated only in the PD780024A Subseries. 2. Incorporated only in the PD780024AY Subseries. Remark The internal ROM and RAM capacities vary depending on the product.
Data Sheet U14042EJ4V0DS
15
PD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
3. PIN FUNCTIONS
3.1 Port Pins (1/2)
Pin Name I/O Function After Reset P00 to P02 I/O Port 0 4-bit I/O port P03 Input/output can be specified in 1-bit units. An on-chip pull-up resistor can be used by setting software. Input Port 1 8-bit input only port P20 P21 P22 P23 P24 P25 P30 P31 P32 P33 P34 P35 P36 P40 to P47 I/O Port 4 8-bit I/O port Input/output can be specified in 1-bit units. An on-chip pull-up resistor can be used by setting software. The interrupt request flag (KRIF) is set to 1 by falling edge detection. Input An on-chip pull-up resistor can be used by setting software. I/O Port 3 7-bit I/O port Input/output can be specified in 1-bit units. N-ch open-drain I/O port An on-chip pull-up resistor can be specified by the mask option. LEDs can be driven directly. SCL0Note 1 SI31Note 2 SO31Note 2 SCK31Note 2 AD0 to AD7 SDA0Note 1 Input I/O Port 2 6-bit I/O port Input/output can be specified in 1-bit units. An on-chip pull-up resistor can be used by setting software. RxD0 TxD0 ASCK0 -- Input SI30 SO30 SCK30 Input Input Alternate Function INTP0 to INTP2 INTP3/ADTRG
P10 to P17
ANI0 to ANI7
P50 to P57
I/O
Port 5 8-bit I/O port LEDs can be driven directly. Input/output can be specified in 1-bit units. An on-chip pull-up resistor can be used by setting software.
Input
A8 to A15
P64 P65 P66 P67
I/O
Port 6 4-bit I/O port Input/output can be specified in 1-bit units. An on-chip pull-up resistor can be used by setting software.
Input
RD WR WAIT ASTB
Notes 1. SDA0 and SCL0 are incorporated only in the PD780024AY Subseries. 2. SI31, SO31, and SCK31 are incorporated only in the PD780024A Subseries.
16
Data Sheet U14042EJ4V0DS
PD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
3.1 Port Pins (2/2)
Pin Name I/O Function After Reset P70 P71 P72 P73 P74 P75 I/O Port 7 6-bit I/O port Input/output can be specified in 1-bit units. An on-chip pull-up resistor can be used by setting software. TI51/TO51 PCL BUZ Input Alternate Function TI00/TO0 TI01 TI50/TO50
3.2 Non-Port Pins (1/2)
Pin Name I/O Function After Reset INTP0 INTP2 INTP2 INTP3 SI30 SI31Note 1 SO30 SO31Note 1 SDA0Note 2 SCK30 SCK31Note 1 SCL0Note 2 RxD0 TxD0 ASCK0 TI00 Input Output Input Input Serial data input for asynchronous serial interface Serial data output for asynchronous serial interface Serial clock input for asynchronous serial interface External count clock input to 16-bit timer/event counter 0 Capture trigger input to capture register 01 (CR01) of 16-bit timer/event counter 0 TI01 TI50 TI51 TO0 TO50 TO51 PCL BUZ AD0 to AD7 A8 to A15 RD WR WAIT ASTB Input Output Output Output I/O Output Output Output Capture trigger input to capture register 00 (CR00) of 16-bit timer/event counter 0 External count clock input to 8-bit timer/event counter 50 External count clock input to 8-bit timer/event counter 51 16-bit timer/event counter 0 output 8-bit timer/event counter 50 output (also used for 8-bit PWM output) 8-bit timer/event counter 51 output (also used for 8-bit PWM output) Clock output (for trimming of main system clock and subsystem clock) Buzzer output Lower address/data bus for expanding memory externally Higher address bus for expanding memory externally Strobe signal output for reading from external memory Strobe signal output for writing to external memory Wait insertion at external memory access Strobe output that externally latches address information output to ports 4 and 5 to access external memory Input Input Input Input Input Input Input Input Input P71 P72/TO50 P73/TO51 P70/TI00 P72/TI50 P73/TI51 P74 P75 P40 to P47 P50 to P57 P64 P65 P66 P67 Input Input Input Input I/O I/O Serial Interface serial data input/output Serial interface serial clock input/output Input Input Output Serial interface serial data output Input Input Serial interface serial data input Input Input External interrupt request input for which the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified Input Alternate Function P00 P01 P02 P03/ADTRG P20 P34 P21 P35 P32 P22 P36 P33 P23 P24 P25 P70/TO0
Notes 1. SI31, SO31, and SCK31 are incorporated only in the PD780024A Subseries. 2. SDA0 and SCL0 are incorporated only in the PD780024AY Subseries.
Data Sheet U14042EJ4V0DS
17
PD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
3.2 Non-Port Pins (2/2)
Pin Name I/O Function After Reset ANI0 to ANI7 ADTRG AVREF AVDD AVSS RESET X1 X2 XT1 XT2 VDD0 VSS0 VDD1 VSS1 IC NC
Note
Alternate Function P10 to P17 P03/INTP3 -- -- -- -- -- -- -- -- -- -- -- -- -- --
Input Input Input -- -- Input Input -- Input -- -- -- -- -- -- --
A/D converter analog input A/D converter trigger signal input A/D converter reference voltage input A/D converter analog power supply. Set potential to that of VDD0 or VDD1 A/D converter ground potential. Set potential to that of VSS0 or VSS1 System reset input Connecting crystal resonator for main system clock oscillation
Input Input -- -- -- -- -- --
Connecting crystal resonator for subsystem clock oscillation
-- --
Positive power supply for ports Ground potential of ports Positive power supply (except ports) Ground potential (except ports) Internally connected. Connect directly to VSS0 or VSS1. Not internally connected. Leave open.
-- -- -- -- -- --
Note
NC pins are incorporated only in the 73-pin plastic FBGA.
18
Data Sheet U14042EJ4V0DS
PD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
3.3 Pin I/O Circuits and Recommended Connection of Unused Pins The I/O circuit type of each pin and recommended connection of unused pins are shown in Table 3-1. For the I/O circuit configuration of each type, see Figure 3-1. Table 3-1. Types of Pin I/O Circuits
Pin Name P00/INTP0 to P02/INTP2 P03/INTP3/ADTRG P10/ANI0 to P17/ANI7 P20/S130 P21/SO30 P22/SCK30 P23/RxD0 P24/TxD0 P25/ASCK0 P30, P31 P32, P33 (PD780024A Subseries only) P32/SDA0 (PD780024AY Subseries only) P33/SCL0 (PD780024AY Subseries only) P34/SI31Note P35/SO31Note P36/SCK31Note P40/AD0 to P47/AD7 P50/A8 to P57/A15 P64/RD P65/WR P66/WAIT P67/ASTB P70/TI00/TO0 P71/TI01 P72/TI50/TO50 P73/TI51/TO51 P74/PCL P75/BUZ RESET XT1 XT2 AVDD AVREF AVSS IC -- 2 16 -- Input -- Connect directly to VDD0 or VDD1. Leave open. Connect to directly VDD0 or VDD1. Connect to directly VSS0 or VSS1. 5-H 8-C 8-C 5-H 8-C 5-H Input: Independently connect to VDD0, VDD1, VSS0, or VSS1 via a resistor. Output: Leave open. Input: Independently connect to VDD0 or VDD1 via a resistor. Output: Leave open. Input: Independently connect to VDD0, VDD1, VSS0, or VSS1 via a resistor. Output: Leave open. 5-H 8-C 13-Q 13-S 13-R Input: Connect directly to VSS0 or VSS1. Output: Leave open at low-level output. 25 8-C 5-H 8-C Input I/O I/O Circuit Type 8-C I/O I/O Recommended Connection of Unused Pins Input: Independently connect to VSS0 or VSS1 via a resistor. Output: Leave open. Connect directly to VDD0, VDD1, VSS0, or VSS1 via a resistor. Input: Independently connect to VDD0, VDD1, VSS0, or VSS1 via a resistor. Output: Leave open.
Note
SI31, SO31, and SCK31 are incorporated only in the PD780024A Subseries.
Data Sheet U14042EJ4V0DS
19
PD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
Figure 3-1. Pin I/O Circuits
TYPE 2
TYPE 13-R
IN/OUT Data Output disable IN VSS0 N-ch
Schmitt-triggered input with hysteresis characteristics
TYPE 5-H
VDD0
TYPE 13-S

Mask option
VDD0 IN/OUT
Pull-up enable Data
P-ch VDD0 P-ch
Data Output disable
N-ch
VSS0 IN/OUT Output disable Input enable TYPE 8-C VDD0 Feedback cut-off Pull-up enable Data P-ch VDD0 P-ch IN/OUT Output disable N-ch VSS0 XT1 XT2 P-ch TYPE 16 N-ch VSS0
TYPE 13-Q

VDD0 Mask option IN/OUT
TYPE 25
P-ch Comparator
+ -
Data Output disable
N-ch VSS0
N-ch VSS0 VREF (threshold voltage) Input enable
IN
Input enable
20
Data Sheet U14042EJ4V0DS
PD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
4. MEMORY SPACE
Figure 4-1 shows the memory map of the PD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, and 780024AY. Figure 4-1. Memory Map
FFFFH Special function registers (SFR) 256 x 8 bits FF00H FEFFH FEE0H FEDFH
General-purpose registers 32 x 8 bits
Internal high-speed RAMNote mmmmH mmmmH - 1
Data memory space
nnnnH Reserved 1000H 0FFFH F800H F7FFH CALLF entry area 0800H 07FFH External memory Program area 0080H 007FH CALLT table area 0040H 003FH Vector table area 0000H 0000H Program area
Program memory space nnnnH + 1 nnnnH
Internal ROM
Note
Note
The internal ROM and internal high-speed RAM capacities vary depending on the product (see the following table).
Part Number Last Address of Internal ROM nnnnH 1FFFH 3FFFH 5FFFH 7FFFH FB00H Start Address of Internal High-Speed RAM mmmmH FD00H
PD780021A, 780021AY PD780022A, 780022AY PD780023A, 780023AY PD780024A, 780024AY
Data Sheet U14042EJ4V0DS
21
PD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
5. PERIPHERAL HARDWARE FUNCTION FEATURES
5.1 Ports The following 3 types of I/O ports are available. * CMOS input (port 1): * CMOS I/O (ports 0, 2, 4 to 7, P34 to P36): * N-channel open-drain I/O (P30 to P33): Total: 8 39 4 51 Table 5-1. Port Functions
Name Port 0 Pin Name P00 to P03 Function I/O port. Input/output can be specified in 1-bit units. An on-chip pull-up resistor can be used by setting software. Input-only port. I/O port. Input/output can be specified in 1-bit units. An on-chip pull-up resistor can be used by setting software. N-channel open-drain I/O port. Input/output can be specified in 1-bit units. A pull-up resistor can be specified by mask option. LEDs can be driven directly. I/O port. Input/output can be specified in 1-bit units. An on-chip pull-up resistor can be used by setting software. I/O port. Input/output can be specified in 1-bit units. An on-chip pull-up resistor can be used by setting software. The interrupt request flag (KRIF) is set to 1 by falling edge detection. Port 5 P50 to P57 I/O port. Input/output can be specified in 1-bit units. An on-chip pull-up resistor can be used by setting software. LEDs can be driven directly. I/O port. Input/output can be specified in 1-bit units. An on-chip pull-up resistor can be used by setting software. I/O port. Input/output can be specified in 1-bit units. An on-chip pull-up resistor can be used by setting software.
Port 1 Port 2
P10 to P17 P20 to P25
Port 3
P30 to P33
P34 to P36
Port 4
P40 to P47
Port 6
P64 to P67
Port 7
P70 to P75
22
Data Sheet U14042EJ4V0DS
PD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
5.2 Clock Generator A system clock generator is incorporated. The minimum instruction execution time can be changed. * Expanded-specification products of PD780021A, 780022A, 780023A, 780024A 0.166 s/0.333 s/0.666 s/1.33 s/2.66 s (@12 MHz, VDD = 4.5 to 5.5 V operation with main system clock) 122 s (@32.768 kHz, VDD = 4.0 to 5.5 V operation with subsystem clock) * PD780021AY, 780022AY, 780023AY, 780024AY, and conventional products of PD780021A, 780022A, 780023A, 780024A 0.238 s/0.48 s/0.95 s/1.91 s/3.81 s (@8.38 MHz, VDD = 4.0 to 5.5 V operation with main system clock) 122 s (@32.768 kHz, VDD = 4.0 to 5.5 V operation with subsystem clock) Figure 5-1. Clock Generator Block Diagram
XT1 XT2
Subsystem clock oscillator
fXT Watch timer, clock output function Prescaler 1
X1 X2
Main system clock oscillator
Prescaler fX fX 2 fX 22 fX 23 fX 24
2 fXT 2
Clock to peripheral hardware
STOP
Selector
Standby controller
Wait controller
CPU clock (fCPU)
HALT
Data Sheet U14042EJ4V0DS
23
PD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
5.3 Timer/Counter Five timer/counter channels are incorporated. * 16-bit timer/event counter: 1 channel * 8-bit timer/event counter: * Watch timer: * Watchdog timer: 2 channels 1 channel 1 channel Table 5-2. Operations of Timer/Event Counter
16-Bit Timer/ Event Counter 0 Operation mode Interval timer External event counter Function Timer outputs PPG outputs PWM output Pulse width measurement Square wave outputs Interrupt sources 1 1 -- 2 inputs 1 2 2 -- 2 -- 2 2 -- -- -- -- -- 2 -- -- -- -- -- 1 1 channel 1 channel 2 channels 2 channels 1 channelNote 1 -- 1 channelNote 2 -- 8-Bit Timer/ Event Counters 50, 51 Watch Timer Watchdog Timer
Notes 1. The watch timer can perform both watch timer and interval timer functions at the same time. 2. The watchdog timer has watchdog timer and interval timer functions. However, use the watchdog timer by selecting either the watchdog timer function or the interval timer function.
24
Data Sheet U14042EJ4V0DS
PD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
Figure 5-2. Block Diagram of 16-Bit Timer/Event Counter 0
Internal bus
Selector
INTTM00
Selector
TI01/P71
Noise eliminator
16-bit capture/compare register 00 (CR00) Match
Selector
fX fX/22 fX/26
16-bit timer counter 0 (TM0) Match
Clear
Output controller
TO0/TI00/P70Note
fX/23
Noise eliminator Noise eliminator
TI00/TO0/P70Note
16-bit capture/compare register 01 (CR01)
Selector
INTTM01
Internal bus
Note
TI00 input and TO0 output cannot be used at the same time.
Data Sheet U14042EJ4V0DS
25
PD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
Figure 5-3. Block Diagram of 8-Bit Timer/Event Counter 50
Internal bus
Mask circuit
8-bit compare register 50 (CR50) TI50/TO50/P72 fX fX/22 fX/24 fX/26 fX/28 fX/210 Match
Selector
INTTM50
Selector
Note 1
8-bit timer OVF counter 50 (TM50) Clear
Selector
S Q INV R
Note 2
TO50/TI50/P72
3 Selector
S R
Level inversion
TCL502 TCL501 TCL500 Timer clock selection register 50 (TCL50)
TCE50 TMC506 TMC504 LVS50 LVR50 TMC501 TOE50 Timer mode control register 50 (TMC50) Internal bus
Figure 5-4. Block Diagram of 8-Bit Timer/Event Counter 51
Internal bus
Mask circuit
8-bit compare register 51 (CR51) TI51/TO51/P73 fX/2 fX/23 fX/25 fX/27 fX/29 fX/211 Match
Selector
Selector
INTTM51
Note 1
8-bit timer counter 51 (TM51)
OVF
Selector
S Q INV R
Note 2
TO51/TI51/P73
Clear 3 Selector S R
Level inversion
TCL512 TCL511 TCL510 Timer clock selection register 51 (TCL51)
TCE51 TMC516 TMC514 LVS51 LVR51 TMC511 TOE51 Timer mode control register 51 (TMC51) Internal bus
Notes 1. Timer output F/F 2. PWM output F/F
26
Data Sheet U14042EJ4V0DS
PD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
Figure 5-5. Watch Timer Block Diagram
Clear
Selector
fX/2
7
fW fW 24
9-bit prescaler fW 25 fW 26 fW 27 fW 28 fW 29
Selector
5-bit counter Clear
INTWT
fXT
INTWTI
WTM7 WTM6 WTM5 WTM4 WTM1 WTM0 Watch timer mode control register (WTM) Internal bus
Figure 5-6. Watchdog Timer Block Diagram
fX Clock input controller Divided clock selector
fX/28
Divider
Output controller
INTWDT RESET
RUN
Division mode selector
3 WDT mode signal
OSTS2 OSTS1 OSTS0
Oscillation stabilization time selection register (OSTS)
WDCS2 WDCS1 WDCS0
RUN WDTM4 WDTM3
Watchdog timer clock selection register (WDCS)
Watchdog timer mode register (WDTM)
Internal bus
Data Sheet U14042EJ4V0DS
27
PD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
5.4 Clock Output/Buzzer Output Controller A clock output/buzzer output controller is incorporated. Clocks with the following frequencies can be output as clock output. * Expanded-specification products of PD780021A, 780022A, 780023A, 780024A * 93.75 kHz/187.5 kHz/375 kHz/750 kHz/1.25 MHz/3 MHz/6 MHz/12 MHz (@12 MHz operation with main system clock) * 32.768 kHz (@32.768 kHz operation with subsystem clock) * PD780021AY, 780022AY, 780023AY, 780024AY, and conventional products of PD780021A, 780022A, 780023A, 780024A * 65.5 kHz/131 kHz/262 kHz/524 kHz/1.05 MHz/2.10 MHz/4.19 MHz/8.38 MHz (@8.38 MHz operation with main system clock) * 32.768 kHz (@32.768 kHz operation with subsystem clock) Clocks with the following frequencies can be output as buzzer output. * Expanded-specification products of PD780021A, 780022A, 780023A, 780024A 1.46 kHz/2.93 kHz/5.86 kHz/11.7 kHz (@12 MHz operation with main system clock) * PD780021AY, 780022AY, 780023AY, 780024AY, and conventional products of PD780021A, 780022A, 780023A, 780024A 1.02 kHz/2.05 kHz/4.10 kHz/8.19 kHz (@8.38 MHz operation with subsystem clock) Figure 5-7. Block Diagram of Clock Output/Buzzer Output Control Circuit
fX
Prescaler 8 4 fX/210 to fX/213
Selector
BUZ/P75
BZOE fX to fX/27
Selector
BCS0, BCS1
Clock controller CLOE
PCL/P74
fXT
BZOE
BCS1
BCS0
CLOE
CCS3
CCS2
CCS1
CCS0
Clock output selection register (CKS) Internal bus
28
Data Sheet U14042EJ4V0DS
PD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
5.5 A/D Converter An A/D converter consisting of eight 8-bit resolution channels is incorporated. The following two A/D conversion operation startup methods are available. * Hardware start * Software start Figure 5-8. A/D Converter Block Diagram
Series resistor string ANI0/P10 ANI1/P11 ANI2/P12 ANI3/P13 ANI4/P14 ANI5/P15 ANI6/P16 ANI7/P17 Successive approximation register (SAR) AVSS Selector Tap selector Sample & hold circuit Voltage comparator AVDD AVREF
INTP3/ADTRG/P03
Edge detector
Controller
INTAD
Edge detector
A/D conversion result register (ADCR0) INTP3 Internal bus
Data Sheet U14042EJ4V0DS
29
PD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
5.6 Serial Interface Three serial interface channels are incorporated. * PD780024A Subseries Serial interface UART0: Serial interface SIO30, SIO31: * PD780024AY Subseries Serial interface UART0: Serial interface SIO30: Serial interface IIC0 (1) Serial interface UART0 Serial interface UART0 has two modes: asynchronous serial interface (UART) mode and infrared data transfer mode. * Asynchronous serial interface (UART) mode This mode enables full-duplex operation wherein one byte of data starting from the start bit is transmitted and received. The on-chip UART-dedicated baud-rate generator enables communication using a wide range of selectable baud rates. In addition, a baud rate can also be defined by dividing the clock input to the ASCK0 pin. The UART-dedicated baud-rate generator can also be used to generate a MIDI-standard baud rate (31.25 kbps). * Infrared data transfer mode This mode enables pulse output and pulse reception in data format. This mode can be used for office equipment applications such as personal computers. Figure 5-9. Block Diagram of Serial Interface UART0 1 channel 1 channel 1 channel 1 channel 2 channels
Internal bus Asynchronous serial interface mode register 0 (ASIM0) TXE0 RXE0 PS01 PS00 CL0 SL0 ISRM0 IRDAM0
Receive RXB0 buffer register 0
RxD0/P23
RX0 Receive
shift register 0
Asynchronous serial interface status register 0 (ASIS0) TXS0 Transmit shift PE0 FE0 OVE0
register 0
TxD0/P24
Receive controller (parity check) Transmit
INTSER0 controller INTSR0
(parity addition)
INTST0
Baud rate generator
P25/ASCK0 fX/2 to fX/27
30
Data Sheet U14042EJ4V0DS
PD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
(2) Serial interface SIO3n Serial interface SIO3n has one mode: 3-wire serial I/O mode. * 3-wire serial I/O mode (fixed as MSB first) This is an 8-bit data transfer mode using three lines: a serial clock line (SCK3n), serial output line (SO3n), and serial input line (SI3n). Since simultaneous transmit and receive operations are enabled in the 3-wire serial I/O mode, the processing time for data transfer is reduced. The first bit in 8-bit data in the serial transfer is fixed as MSB. The 3-wire serial I/O mode is useful for connection to peripheral I/O devices, and display controllers, etc., that include a clocked serial interface. Figure 5-10. Block Diagram of Serial Interface SIO3n
Internal bus 8 SI3n Serial I/O shift register 3n (SIO3n)
SO3n SCK3n Serial clock counter Serial clock controller Interrupt request signal generator INTCSI3n fX/23 fX/24 fX/25
Selector
Remark PD780024A Subseries: n = 0, 1
PD780024AY Subseries: n = 0
Data Sheet U14042EJ4V0DS
31
PD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
(3) Serial interface IIC0 (PD780024AY Subseries only) Serial interface IIC0 has one mode: I2C (Inter IC) bus mode (supporting multimaster). * I2C bus mode (supporting multimaster) This is an 8-bit data transfer mode using two lines: a serial clock line (SCL0) and a serial data bus line (SDA0). This mode complies with the I2C bus format, and can output a "start condition", "data", and a "stop condition" during transmission via the serial data bus. This data is automatically detected by hardware during reception. Since SCL0 and SDA0 are open-drain outputs in IIC0, pull-up resistors for the serial clock line and the serial data bus line are required. Figure 5-11. Block Diagram of Serial Interface IIC0
Internal bus IIC status register 0 (IICS0)
MSTS0 ALD0 EXC0 COI0 TRC0 ACKD0 STD0 SPD0
IIC control register 0 (IICC0) SDA0/P32 Noise eliminator Slave address register 0 (SVA0) Match signal
IICE0 LREL0 WREL0 SPIE0 WTIM0 ACKE0 STT0 SPT0
CLEAR SET SO0 latch D CL00
IIC shift register 0 (IIC0)
N-ch opendrain output
Data hold time corrector
Acknowledge detector
Wake-up controller Acknowledge detector Start condition detector
SCL0/P33 Noise eliminator
Stop condition detector Interrupt request signal generator
Serial clock counter
INTIIC0
Serial clock controller N-ch open-drain output fX Prescaler
Serial clock wait controller
CLD0 DAD0 SMC0 DFC0 CL00
IIC transfer clock select register 0 (IICCL0)
Internal bus
32
Data Sheet U14042EJ4V0DS
PD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
6. INTERRUPT FUNCTIONS
A total of 20 interrupt sources are provided, divided into the following three types. * Non-maskable: 1 * Maskable: * Software: 18 1 Table 6-1. Interrupt Source List
Interrupt Type Nonmaskable Maskable Default PriorityNote 1 -- Name INTWDT Interrupt Source Trigger Watchdog timer overflow (with watchdog timer mode 1 selected) Watchdog timer overflow (with interval timer mode selected) Pin input edge detection External 0006H 0008H 000AH 000CH Serial interface UART0 reception error generation End of serial interface UART0 reception End of serial interface UART0 transmission End of serial interface SIO30 transfer End of serial interface SIO31 transfer [Only for PD780024A Subseries] 10 INTIIC0 End of serial interface IIC0 transfer [Only for PD780024AY Subseries] Reference time interval signal from watch timer Match between TM0 and CR00 (when CR00 is specified as compare register) Detection of TI01 valid edge (when CR00 is specified as capture register) 13 INTTM01 Match between TM0 and CR01 (when CR01 is specified as compare register) Detection of TI00 valid edge (when CR01 is specified as capture register) Match between TM50 and CR50 Match between TM51 and CR51 End of A/D conversion Watch timer overflow Port 4 falling edge detection BRK instruction execution External -- 001EH 0018H Internal 000EH (B) Internal/ External Internal
Vector Table Address Basic Configuration TypeNote 2
0004H
(A)
0
INTWDT
(B)
1 2 3 4 5
INTP0 INTP1 INTP2 INTP3 INTSER0
(C)
6 7 8 9
INTSR0 INTST0 INTCSI30 INTCSI31
0010H 0012H 0014H 0016H
11 12
INTWTI INTTM00
001AH 001CH
14 15 16 17 18 Software --
INTTM50 INTTM51 INTAD0 INTWT INTKR BRK
0020H 0022H 0024H 0026H 0028H 003EH (D) (E)
Notes 1. The default priority is the priority when several maskable interrupt requests are generated at the same time. 0 is the highest, and 18 is the lowest. 2. Basic configuration types (A) to (E) correspond to (A) to (E) in Figure 6-1. Remark The watchdog timer interrupt (INTWDT) can be selected from a non-maskable interrupt or a maskable interrupt (internal).
Data Sheet U14042EJ4V0DS
33
PD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
Figure 6-1. Basic Configuration of Interrupt Function (1/2) (A) Internal non-maskable interrupt
Internal bus
Interrupt request
Priority controller
Vector table address generator Standby release signal
(B) Internal maskable interrupt
Internal bus
MK
IE
PR
ISP
Interrupt request
IF
Priority controller
Vector table address generator Standby release signal
(C) External maskable interrupt (INTP0 to INTP3)
Internal bus
External interrupt edge enable register (EGP, EGN)
MK
IE
PR
ISP
Interrupt request
Edge detector
IF
Priority controller
Vector table address generator Standby release signal
34
Data Sheet U14042EJ4V0DS
PD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
Figure 6-1. Basic Configuration of Interrupt Function (2/2) (D) External maskable interrupt (INTKR)
Internal bus
MK
IE
PR
ISP
Interrupt request
Falling edge detector
IF
Priority controller
Vector table address generator Standby release signal
(E) Software interrupt
Internal bus
Interrupt request
Vector table address generator
IF: IE: ISP: MK: PR:
Interrupt request flag Interrupt enable flag In-service priority flag Interrupt mask flag Priority specification flag
Data Sheet U14042EJ4V0DS
35
PD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
7. EXTERNAL DEVICE EXPANSION FUNCTION
The external device expansion function is for connecting external devices to areas other than the internal ROM, RAM, and SFR areas. Ports 4 to 6 are used for external device connection.
8. STANDBY FUNCTION
The following two standby modes are available for further reduction of system power consumption. * HALT mode: In this mode, the CPU operation clock is stopped. The average power consumption can be reduced by intermittent operation by combining this mode with the normal operation mode. * STOP mode: In this mode, oscillation of the main system clock is stopped. All the operations performed on the main system clock are suspended, and only the subsystem clock is used, resulting in extremely small power consumption. This can be used only when the main system clock is operating (the subsystem clock oscillation cannot be stopped). Figure 8-1. Standby Function
CSS = 1 Main system clock operation STOP instruction Interrupt request HALT mode Clock supply for CPU is stopped, oscillation is maintained CSS = 0 HALT instruction Interrupt request HALT modeNote Clock supply for CPU is stopped, oscillation is maintained Subsystem clock operationNote HALT instruction
Interrupt request
STOP mode Main system clock operation is stopped
Note
The power consumption can be reduced by stopping the main system clock. When the CPU is operating on the subsystem clock, set bit 7 (MCC) of the processor clock control register (PCC). The STOP instruction cannot be used.
Caution When the main system clock is stopped and the device is operating on the subsystem clock, wait until the oscillation stabilization time has been secured by the program before switching back to the main system clock.
9. RESET FUNCTION
The following two reset methods are available. * External reset by RESET signal input * Internal reset by watchdog timer program loop time detection
10. MASK OPTION
Table 10-1 Pin Mask Option Selection
Subseries Name Pins P30 to P33 P30 and P31 Mask Option An on-chip pull-up resistor can be specified in 1-bit units.
PD780024A Subseries PD780024AY Subseries
The mask option can be used to specify the connection of an on-chip pull-up resistor to P30 to P33Note, in 1-bit units. Note The PD780024AY Subseries has P30 and P31 only.
Data Sheet U14042EJ4V0DS
36
PD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
11. INSTRUCTION SET
(1) 8-bit instructions MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, MULU, DIVUW, INC, DEC, ROR, ROL, RORC, ROLC, ROR4, ROL4, PUSH, POP, DBNZ
2nd Operand 1st Operand A #byte A r
[HL + byte]
Note
sfr
saddr
!addr16
PSW
[DE]
[HL]
[HL + B] [HL + C]
$addr16
1
None
ADD ADDC SUB SUBC AND OR XOR CMP
MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP
MOV XCH
MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP
MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP
MOV
MOV XCH
MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP
MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP
ROR ROL RORC ROLC
r
MOV
MOV ADD ADDC SUB SUBC AND OR XOR CMP
INC DEC
B, C sfr saddr MOV MOV ADD ADDC SUB SUBC AND OR XOR CMP !addr16 PSW MOV MOV MOV MOV MOV MOV MOV
DBNZ
DBNZ
INC DEC
PUSH POP
[DE] [HL]
ROR4 ROL4
[HL + byte] [HL + B] [HL + C] X C
MOV
MULU DIVUW
Note
Except r = A
Data Sheet U14042EJ4V0DS
37
PD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
(2) 16-bit instructions MOVW, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW
2nd Operand 1st Operand AX #word ADDW SUBW CMPW MOVW MOVW MOVW MOVW MOVWNote MOVW MOVW MOVW MOVW AX rpNote MOVW XCHW sfrp MOVW saddrp MOVW !addr16 MOVW SP MOVW None
rp sfrp saddrp !addr16 SP
INCW, DECW PUSH, POP
Note
Only when rp = BC, DE or HL
(3) Bit manipulation instructions MOV1, AND1, OR1, XOR1, SET1, CLR1, NOT1, BT, BF, BTCLR
2nd Operand 1st Operand A.bit A.bit sfr.bit saddr.bit PSW.bit [HL].bit CY MOV1 $addr16 BT BF BTCLR BT BF BTCLR BT BF BTCLR BT BF BTCLR BT BF BTCLR None SET1 CLR1 SET1 CLR1 SET1 CLR1 SET1 CLR1 SET1 CLR1
sfr.bit
MOV1
saddr.bit
MOV1
PSW.bit
MOV1
[HL].bit
MOV1
CY
MOV1 AND1 OR1 XOR1
MOV1 AND1 OR1 XOR1
MOV1 AND1 OR1 XOR1
MOV1 AND1 OR1 XOR1
MOV1 AND1 OR1 XOR1
SET1 CLR1 NOT1
(4) Call instructions/branch instructions CALL, CALLF, CALLT, BR, BC, BNC, BZ, BNZ, BT, BF, BTCLR, DBNZ
2nd Operand 1st Operand Basic instruction Compound instruction BR AX !addr16 CALL BR !addr11 CALLF [addr5] CALLT $addr16 BR, BC, BNC BZ, BNZ BT, BF BTCLR DBNZ
(5) Other instructions ADJBA, ADJBS, BRK, RET, RETI, RETB, SEL, NOP, EI, DI, HALT, STOP
38
Data Sheet U14042EJ4V0DS
PD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
12. ELECTRICAL SPECIFICATIONS
12.1 Expanded-Specification Products of PD780021A, 780022A, 780023A, 780024A Absolute Maximum Ratings (TA = 25C)
Parameter Supply voltage
Symbol VDD AVDD AVREF AVSS
Conditions
Ratings -0.3 to +6.5 -0.3 to VDD + 0.3Note -0.3 to VDD + 0.3Note -0.3 to +0.3
Unit V V V V V
Input voltage
VI1
P00 to P03, P10 to P17, P20 to P25, P34 to P36, P40 to P47, P50 to P57, P64 to P67, P70 to P75, X1, X2, XT1, XT2, RESET
-0.3 to VDD +
0.3Note
VI2
P30 to P33
N-ch open-drain Without pull-up resistor With pull-up resistor
-0.3 to + 6.5 -0.3 to VDD + 0.3Note -0.3 to VDD + 0.3Note 0.3Note
V V V V
Output voltage Analog input voltage
VO VAN P10 to P17 Analog input pin
AVSS - 0.3 to AVREF0 + and -0.3 to VDD + 0.3Note -10 -15 -15 20
Output current, high
IOH
Per pin Total for P00 to P03, P40 to P47, P50 to P57, P64 to P67, P70 to P75 Total for P20 to P25, P30 to P36
mA mA mA mA
Output current, low
IOL
Per pin for P00 to P03, P20 to P25, P34 to P36, P40 to P47, P64 to P67, P70 to P75 Per pin for P30 to P33, P50 to P57 Total for P00 to P03, P40 to P47, P64 to P67, P70 to P75 Total for P20 to P25 Total for P30 to P36 Total for P50 to P57
30 50
mA mA
20 100 100 -40 to +85
mA mA mA C
Operating ambient temperature Storage temperature
TA
Tstg
-65 to +150
C
Note
6.5 V or below Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded.
Caution
Remark
Unless otherwise specified, the characteristic of alternate-function pins are the same as those of port pins.
Data Sheet U14042EJ4V0DS
39
PD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
Capacitance (TA = 25C, VDD = VSS = 0 V)
Parameter Input capacitance I/O capacitance CIO Symbol CIN f = 1 MHz Unmeasured pins returned to 0 V. f = 1 MHz Unmeasured pins returned to 0 V. P00 P34 P50 P70 to to to to P03, P20 to P25, P36, P40 to P47, P57, P64 to P67, P75 15 pF Conditions MIN. TYP. MAX. 15 Unit pF
P30 to P33
20
pF
Remark
Unless otherwise specified, the characteristic of alternate-function pins are the same as those of port pins.
Main System Clock Oscillator Characteristics (TA = -40 to +85C, VDD = 1.8 to 5.5 V)
Resonator Ceramic resonator IC X2 X1 Recommended Circuit Parameter Oscillation frequency (fX) Oscillation stabilization Crystal resonator
C2 C1
Note 1
Conditions 4.5 V VDD 5.5 V 3.0 V VDD < 4.5 V 1.8 V VDD < 3.0 V After VDD reaches
MIN. 1.0 1.0 1.0
TYP.
MAX. 12.0 8.38 5.0 4
Unit MHz
C2
C1
ms
timeNote 2
oscillation voltage range MIN. 4.5 V VDD 5.5 V 3.0 V VDD < 4.5 V 1.8 V VDD < 3.0 V 4.0 V VDD 5.5 V 1.8 V VDD < 4.0 V 4.5 V VDD 5.5 V 3.0 V VDD < 4.5 V 1.8 V VDD < 3.0 V 4.5 V VDD 5.5 V 3.0 V VDD < 4.5 V 1.8 V VDD < 3.0 V 1.0 1.0 1.0 38 50 85 1.0 1.0 1.0 12.0 8.38 5.0 10 30 12.0 8.38 5.0 500 500 500 ns MHz ms MHz
IC
X2
X1
Oscillation frequency (fX)Note 1 Oscillation stabilization timeNote 2
External clock X2 X1
X1 input frequency (fX)Note 1
X1 input high-/low-level width (tXH, tXL)
Notes 1. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time. 2. Time required to stabilize oscillation after reset or STOP mode release. Cautions 1. When using the main system clock oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. * Keep the wiring length as short as possible. * Do not cross the wiring with the other signal lines. * Do not route the wiring near a signal line through which a high fluctuating current flows. * Always make the ground point of the oscillator capacitor the same potential as VSS1. * Do not ground the capacitor to a ground pattern through which a high current flows. * Do not fetch signals from the oscillator. 2. When the main system clock is stopped and the system is operating on the subsystem clock, wait until the oscillation stabilization time has been secured by the program before switching back to the main system clock.
40
Data Sheet U14042EJ4V0DS
PD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
Subsystem Clock Oscillator Characteristics (TA = -40 to +85C, VDD = 1.8 to 5.5 V)
Resonator Crystal resonator Recommended Circuit
XT2
R C4
Parameter Oscillation frequency (fXT)Note 1 Oscillation stabilization timeNote 2 XT1 input frequency (fXT)Note 1 XT1 input high-/low-level width (tXTH , tXTL)
Conditions
MIN. 32
TYP. 32.768
MAX. 35
Unit kHz
XT1 IC
C3
4.0 V VDD 5.5 V 1.8 V VDD < 4.0 V 32
1.2
2 10 38.5
s
External clock
kHz
XT2
XT1
12
15
s
Notes 1. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time. 2. Time required to stabilize oscillation after VDD reaches oscillation voltage range MIN. Cautions 1. When using the subsystem clock oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. * Keep the wiring length as short as possible. * Do not cross the wiring with the other signal lines. * Do not route the wiring near a signal line through which a high fluctuating current flows. * Always make the ground point of the oscillator capacitor the same potential as VSS1. * Do not ground the capacitor to a ground pattern through which a high current flows. * Do not fetch signals from the oscillator. 2. The subsystem clock oscillator is designed as a low-amplitude circuit for reducing power consumption, and is more prone to malfunction due to noise than the main system clock oscillator. Particular care is therefore required with the wiring method when the subsystem clock is used. Remark For the resonator selection and oscillator constant, customers are required to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation.
Data Sheet U14042EJ4V0DS
41
PD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
Recommended Oscillator Constant Main system clock: Ceramic resonator (TA = -40 to +85C)
Manufacturer Part Number Frequency (MHz) Murata Mfg. Co., Ltd. CSBFB1M00J58 CSBLA1M00J58 CSTCC2M00G56 CSTLS2M00G56 CSTCC3M58G53 CSTLS3M58G53 CSTCR4M00G53 CSTLS4M00G53 CSTCR4M19G53 CSTLS4M19G53 CSTCR4M91G53 CSTLS4M91G53 CSTCR5M00G53 CSTLS5M00G53 CSTCE8M00G52 CSTLS8M00G53 CSTCE8M38G52 CSTLS8M38G53 CSTCE10M0G52 CSTLS10M0G53 CSTCE12M0G52 CSTLA12M0T55 TDK CCR3.58MC3 CCR4.19MC3 CCR5.0MC3 CCR8.0MC5 CCR8.38MC5 1.00 1.00 2.00 2.00 3.58 3.58 4.00 4.00 4.19 4.19 4.91 4.91 5.00 5.00 8.00 8.00 8.38 8.38 10.00 10.00 12.00 12.00 3.58 4.19 5.00 8.00 8.38 Recommended Circuit Constant C1 (pF) 100 100 On-chip On-chip On-chip On-chip On-chip On-chip On-chip On-chip On-chip On-chip On-chip On-chip On-chip On-chip On-chip On-chip On-chip On-chip On-chip On-chip On-chip On-chip On-chip On-chip On-chip C2 (pF) 100 100 On-chip On-chip On-chip On-chip On-chip On-chip On-chip On-chip On-chip On-chip On-chip On-chip On-chip On-chip On-chip On-chip On-chip On-chip On-chip On-chip On-chip On-chip On-chip On-chip On-chip R1 (k) 2.2 2.2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Oscillation Voltage Range MIN. (V) 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 3.0 3.0 3.0 3.0 4.5 4.5 4.5 4.5 1.8 1.8 1.8 2.0 2.0 MAX. (V) 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5
Caution The oscillator constant is a reference value based on evaluation in specific environments by the resonator manufacturer. If the oscillator characteristics need to be optimized in the actual application, request the resonator manufacturer for evaluation on the implementation circuit. Note that the oscillation voltage and oscillation frequency merely indicate the characteristics of the oscillator. Use the internal operation conditions of the PD780024A Subseries within the specifications of the DC and AC characteristics.
42
Data Sheet U14042EJ4V0DS
PD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
DC Characteristics (TA = -40 to +85C, VDD = 1.8 to 5.5 V)
Parameter Output current, high Output current, low
Symbol IOH Per pin All pins IOL
Conditions
MIN.
TYP.
MAX. -1 -15 10
Unit mA mA mA
Per pin for P00 to P03, P20 to P25, P34 to P36, P40 to P47, P64 to P67, P70 to P75 Per pin for P30 to P33, P50 to P57 Total for P00 to P03, P40 to P47, P64 to P67, P70 to P75 Total for P20 to P25 Total for P30 to P36 Total for P50 to P57
15 20 10 70 70
mA mA mA mA mA V V V V V V V V V V V V V V V V V V V V V V V V V V
Input voltage, high
VIH1
P10 to P17, P21, P24, P35, P40 to P47, P50 to P57, P64 to P67, P74, P75
2.7 V VDD 5.5 V 1.8 V VDD < 2.7 V 2.7 V VDD 5.5 V 1.8 V VDD < 2.7 V 2.7 V VDD 5.5 V 1.8 V VDD < 2.7 V 2.7 V VDD 5.5 V 1.8 V VDD < 2.7 V
0.7VDD 0.8VDD 0.8VDD 0.85VDD 0.7VDD 0.8VDD VDD - 0.5 VDD - 0.2 0.8VDD 0.9VDD 0 0 0 0 0 0 0 0 0 0 0 VDD - 1.0 VDD - 0.5
VDD VDD VDD VDD 5.5 5.5 VDD VDD VDD VDD 0.3VDD 0.2VDD 0.2VDD 0.15VDD 0.3VDD 0.2VDD 0.1VDD 0.4 0.2 0.2VDD 0.1VDD VDD VDD 2.0 0.4 2.0 0.4
VIH2
P00 to P03, P20, P22, P23, P25, P34, P36, P70 to P73, RESET
VIH3
P30 to P33 (N-ch open-drain)
VIH4
X1, X2
VIH5
XT1, XT2
4.0 V VDD 5.5 V 1.8 V VDD < 4.0 V
Input voltage, low
VIL1
P10 to P17, P21, P24, P35, P40 to P47, P50 to P57, P64 to P67, P74, P75
2.7 V VDD 5.5 V 1.8 V VDD < 2.7 V 2.7 V VDD 5.5 V 1.8 V VDD < 2.7 V 4.0 V VDD 5.5 V 2.7 V VDD < 4.0 V 1.8 V VDD < 2.7 V 2.7 V VDD 5.5 V 1.8 V VDD < 2.7 V 4.0 V VDD 5.5 V 1.8 V VDD < 4.0 V
VIL2
P00 to P03, P20, P22, P23, P25, P34, P36, P70 to P73, RESET
VIL3
P30 to P33
VIL4
X1, X2
VIL5
XT1, XT2 4.0 V VDD 5.5 V, IOH = -1 mA
Output voltage, high Output voltage, low
VOH1
1.8 V VDD < 4.0 V, IOH = -100 A VOL1 P30 to P33 P50 to P57 4.0 V VDD 5.5 V, IOL = 15 mA
P00 to P03, P20 to P25, P34 to P36, 4.0 V VDD 5.5 V, P40 to P47, P64 to P67, P70 to P75 VOL2 IOL = 400 A IOL = 1.6 mA
0.5
V
Remark
Unless otherwise specified, the characteristics of alternate-function pins are the same as those of port pins.
Data Sheet U14042EJ4V0DS
43
PD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
DC Characteristics (TA = -40 to +85C, VDD = 1.8 to 5.5 V)
Parameter Input leakage current, high Symbol ILIH1 VIN = VDD Conditions P00 to P03, P10 to P17, P20 to P25, P34 to P36, P40 to P47, P50 to P57, P60 to P67, P70 to P75, RESET X1, X2, XT1, XT2 VIN = 5.5 V VIN = 0 V P30 to P33Note P00 to P03, P10 to P17, P20 to P25, P34 to P36, P40 to P47, P50 to P57, P64 to P67, P70 to P75, RESET X1, X2, XT1, XT2 P30 to P33 VOUT = VDD VOUT = 0 V VIN = 0 V, P30, P31, P32, P33 VIN = 0 V, P00 to P03, P20 to P25, P34 to P36, P40 to P47, P50 to P57, P64 to P67, P70 to P75 15 15 30 30
Note
MIN.
TYP.
MAX. 3
Unit
A
ILIH2 ILIH3 Input leakage current, low ILIL1
20 3 -3
A A A
ILIL2 ILIL3 Output leakage current, high Output leakage current, low Mask option pull-up resistance Software pullup resistance ILOH ILOL R1 R2
-20 -3 3 -3 90 90
A A A A
k k
Note When pull-up resistors are not connected to P30 to P33 (specified by the mask option). Remark Unless otherwise specified, the characteristics of alternate-function pins are the same as those of port pins.
44
Data Sheet U14042EJ4V0DS
PD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
DC Characteristics (TA = -40 to +85C, VDD = 1.8 to 5.5 V)
Parameter Power supply currentNote 1 Symbol IDD1Note 2 Conditions 12.0 MHz VDD = 5.0 V crystal oscillation operating mode 10%Note 3 When A/D converter is stopped When A/D converter is operatingNote 7 When A/D converter is stopped When A/D converter is operatingNote 7 VDD = 3.0 V + 10%Notes 3, 6 When A/D converter is stopped When A/D converter is operatingNote 7 5.00 MHz VDD = 3.0 V 10%Note 3 crystal oscillation operating mode VDD = 2.0 V 10%Note 4 When A/D converter is stopped When A/D converter is operatingNote 7 When A/D converter is stopped When A/D converter is operatingNote 7 IDD2 12.0 MHz VDD = 5.0 V 10%Note 3 crystal oscillation HALT mode 8.38 MHz VDD = 5.0 V 10%Note 3 crystal oscillation HALT mode When peripheral functions are stopped When peripheral functions are operating When peripheral functions are stopped When peripheral functions are operating VDD = 3.0 V + 10%Notes 3, 6 When peripheral functions are stopped When peripheral functions are operating 5.00 MHz VDD = 3.0 V 10%Note 3 crystal oscillation HALT mode VDD = 2.0 V 10%Note 4 When peripheral functions are stopped When peripheral functions are operating When peripheral functions are stopped When peripheral functions are operating
IDD3
MIN.
TYP. 8.5 9.5 5.5 6.5 3 4 2 3 0.4 1.4 2
MAX. 17 19 11 13 6 8 4 6 1.5 4.2 4 10
Unit mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA
8.38 MHz VDD = 5.0 V 10%Note 3 crystal oscillation operating mode
1.1
2.2 4.7
0.5
1 4
0.35
0.7 1.7
0.15
0.4 1.1
32.768 kHz crystal oscillation operating modeNote 5
VDD = 5.0 V 10% VDD = 3.0 V 10% VDD = 2.0 V 10% VDD = 5.0 V 10% VDD = 3.0 V 10% VDD = 2.0 V 10% VDD = 5.0 V 10% VDD = 3.0 V 10% VDD = 2.0 V 10%
40 20 10 30 6 2 0.1 0.05 0.05
80 40 20 60 18 10 30 10 10
A A A A A A A A A
IDD4
32.768 kHz crystal oscillation HALT mode
Note 5
IDD5
XT1 = VDD STOP mode When feedback resistor is not used
Data Sheet U14042EJ4V0DS
45
PD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
Notes 1. Total current through the internal power supply (VDD0, VDD1) (except the current through pull-up resistors of ports). 2. IDD1 includes the peripheral operation current. 3. When the processor clock control register (PCC) is set to 00H. 4. When PCC is set to 02H. 5. When main system clock operation is stopped. 6. The values show the specifications when VDD = 3.0 to 3.3 V. The value in the TYP. column show the specifications when VDD = 3.0 V. 7. Includes the current through the AVDD pin.
46
Data Sheet U14042EJ4V0DS
PD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
AC Characteristics (1) Basic Operation (TA = -40 to +85C, VDD = 1.8 to 5.5 V)
Parameter Cycle time (Min. instruction execution time) Symbol TCY Operating with main system clock Conditions 4.5 V VDD 5.5 V 3.0 V VDD 4.5 V 2.7 V VDD 3.0 V 1.8 V VDD 2.7 V Operating with subsystem clock TI00, TI01 input high-/low-level width TI50, TI51 input frequency TI50, TI51 input high-/low-level width Interrupt request input high-/lowlevel width RESET low-level width tRSL tINTH, tINTL INTP0 to INTP3, P40 to P47 2.7 V VDD 5.5 V 1.8 V VDD < 2.7 V 2.7 V VDD 5.5 V 1.8 V VDD < 2.7 V 1 2 10 20 tTIH5, tTIL5 fTI5 tTIH0, tTIL0 3.0 V VDD 5.5 V 2.7 V VDD < 3.0 V 1.8 V VDD < 2.7 V 2.7 V VDD 5.5 V 1.8 V VDD < 2.7 V 2.7 V VDD 5.5 V 1.8 V VDD < 2.7 V MIN. 0.166 0.238 0.4 1.6 103.9Note 1 2/fsam+0.1Note 2 2/fsam+0.2Note 2 2/fsam+0.5Note 2 0 0 100 1.8 4 275 122 TYP. MAX. 16 16 16 16 125 Unit
s s s s s s s s
MHz kHz ns ns
s s s s
Notes 1. Value when the external clock is used. When a crystal resonator is used, it is 114 s (MIN.). 2. Selection of fsam = fX, fX/4, fX/64 is possible using bits 0 and 1 (PRM00, PRM01) of prescaler mode register 0 (PRM0). However, if the TI00 valid edge is selected as the count clock, the value becomes fsam = fX/8.
Data Sheet U14042EJ4V0DS
47
PD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
TCY vs. VDD (main system clock operation)
16.0 10.0
Cycle time TCY [ S]
5.0
Operation guaranteed range
2.0 1.6 1.0
0.4 0.238 0.166 0.1 0 1.0 1.8 2.0 2.7 3.0 4.0 4.5 5.0 5.5 6.0
Supply voltage VDD [V]
48
Data Sheet U14042EJ4V0DS
PD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
(2) Read/Write Operation (TA = -40 to +85C, VDD = 4.0 to 5.5 V)
Parameter ASTB high-level width Address setup time Address hold time Data input time from address Symbol tASTH tADS tADH tADD1 tADD2 Address output time from RD Data input time from RD tRDAD tRDD1 tRDD2 Read data hold time RD low-level width tRDH tRDL1 tRDL2 Input time from RD to WAIT tRDWT1 tRDWT2 Input time from WR to WAIT WAIT low-level width Write data setup time Write data hold time WR low-level width Delay time from ASTB to RD Delay time from ASTB to WR Delay time from RD to ASTB at external fetch Address hold time from RD at external fetch Write data output time from RD Write data output time from WR Address hold time from WR Delay time from WAIT to RD Delay time from WAIT to WR tRDWD tWRWD tWRADH tWTRD tWTWR 40 10 0.8tCY - 15 0.8tCY 0.8tCY 60 1.2tCY + 30 2.5tCY + 25 2.5tCY + 25 tRDADH 0.8tCY - 15 1.2tCY + 30 tWRWT tWTL tWDS tWDH tWRL1 tASTRD tASTWR tRDAST (0.5 + n)tCY + 10 60 6 (1.5 + 2n)tCY - 15 6 2tCY - 15 0.8tCY - 15 1.2tCY 0 (1.5 + 2n)tCY - 33 (2.5 + 2n)tCY - 33 tCY - 43 tCY - 43 tCY - 25 (2 + 2n)tCY 0 Conditions MIN. 0.3tCY 20 6 (2 + 2n)tCY - 54 (3 + 2n)tCY - 60 100 (2 + 2n)tCY - 87 (3 + 2n)tCY - 93 MAX.
(1/3)
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
ns
ns ns ns ns ns
Caution Remarks
TCY can only be used when the MIN. value is 0.238 s. 1. 2. 3. tCY = TCY/4 n indicates the number of waits. CL = 100 pF (CL indicates the load capacitance of the AD0 to AD7, A8 to A15, RD, WR, WAIT, and ASTB pins.)
Data Sheet U14042EJ4V0DS
49
PD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
(2) Read/Write Operation (TA = -40 to +85C, VDD = 2.7 to 4.0 V) (2/3)
Parameter ASTB high-level width Address setup time Address hold time Input time from address to data Symbol tASTH tADS tADH tADD1 tADD2 Output time from RD to address Input time from RD to data tRDAD tRDD1 tRDD2 Read data hold time RD low-level width tRDH tRDL1 tRDL2 Input time from RD to WAIT tRDWT1 tRDWT2 Input time from WR to WAIT WAIT low-level width Write data setup time Write data hold time WR low-level width Delay time from ASTB to RD Delay time from ASTB to WR Delay time from RD to ASTB at external fetch Hold time from RD to address at external fetch Write data output time from RD Write data output time from WR Hold time from WR to address Delay time from WAIT to RD Delay time from WAIT to WR tRDWD tWRWD tWRADH tWTRD tWTWR 40 20 0.8tCY - 30 0.5tCY 0.5tCY 120 1.2tCY + 60 2.5tCY + 50 2.5tCY + 50 ns ns ns ns ns tRDADH 0.8tCY - 30 1.2tCY + 60 ns tWRWT tWTL tWDS tWDH tWRL1 tASTRD tASTWR tRDAST (0.5 + 2n)tCY + 10 60 10 (1.5 + 2n)tCY - 30 10 2tCY - 30 0.8tCY - 30 1.2tCY 0 (1.5 + 2n)tCY - 40 (2.5 + 2n)tCY - 40 tCY - 75 tCY - 60 tCY - 50 (2 + 2n)tCY 0 Conditions MIN. 0.3tCY 30 10 (2 + 2n)tCY - 108 (3 + 2n)tCY - 120 200 (2 + 2n)tCY - 148 (3 + 2n)tCY - 162 MAX. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Caution Remarks
TCY can only be used when the MIN. value is 0.4 s. 1. 2. 3. tCY = TCY/4 n indicates the number of waits. CL = 100 pF (CL indicates the load capacitance of the AD0 to AD7, AD8 to AD15, RD, WR, WAIT, and ASTB pins.)
50
Data Sheet U14042EJ4V0DS
PD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
(2) Read/Write Operation (TA = -40 to +85C, VDD = 1.8 to 2.7 V) (3/3)
Parameter ASTB high-level width Address setup time Address hold time Input time from address to data Symbol tASTH tADS tADH tADD1 tADD2 Output time from RD to address Input time from RD to data tRDAD tRDD1 tRDD2 Read data hold time RD low-level width tRDH tRDL1 tRDL2 Input time from RD to WAIT tRDWT1 tRDWT2 Input time from WR to WAIT WAIT low-level width Write data setup time Write data hold time WR low-level width Delay time from ASTB to RD Delay time from ASTB to WR Delay time from RD to ASTB at external fetch Hold time from RD to address at external fetch Write data output time from RD Write data output time from WR Hold time from WR to address Delay time from WAIT to RD Delay time from WAIT to WR tRDWD tWRWD tWRADH tWTRD tWTWR 40 40 0.8tCY - 60 0.5tCY 0.5tCY 240 1.2tCY + 120 2.5tCY + 100 2.5tCY + 100 ns ns ns ns ns tRDADH 0.8tCY - 60 1.2tCY + 120 ns tWRWT tWTL tWDS tWDH tWRL1 tASTRD tASTWR tRDAST (0.5 + 2n)tCY + 10 60 20 (1.5 + 2n)tCY - 60 20 2tCY - 60 0.8tCY - 60 1.2tCY 0 (1.5 + 2n)tCY - 92 (2.5 + 2n)tCY - 92 tCY - 350 tCY - 132 tCY - 100 (2 + 2n)tCY 0 Conditions MIN. 0.3tCY 120 20 (2 + 2n)tCY - 233 (3 + 2n)tCY - 240 400 (2 + 2n)tCY - 325 (3 + 2n)tCY - 332 MAX. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Caution Remarks
TCY can only be used when the MIN. value is 1.6 s. 1. 2. 3. tCY = TCY/4 n indicates the number of waits. CL = 100 pF (CL indicates the load capacitance of the AD0 to AD7, AD8 to AD15, RD, WR, WAIT, and ASTB pins.)
Data Sheet U14042EJ4V0DS
51
PD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
(3) Serial Interface (TA = -40 to +85C, VDD = 1.8 to 5.5 V) (a) 3-wire serial I/O mode (SCK3n... Internal clock output)
Parameter SCK3n cycle time Symbol tKCY1 Conditions 4.5 V VDD 5.5 V 3.0 V VDD < 4.5 V 2.7 V VDD < 3.0 V 1.8 V VDD < 2.7 V SCK3n high-/ low-level width SI3n setup time (to SCK3n) tSIK1 tKH1, tKL1 3.0 V VDD 5.5 V 1.8 V VDD < 3.0 V 3.0 V VDD 5.5 V 2.7 V VDD < 3.0 V 1.8 V VDD < 2.7 V SI3n hold time (from SCK3n) Delay time from SCK3n to SO3n output tKSO1 tKSI1 4.5 V VDD 5.5 V 1.8 V VDD < 4.5 V C = 100 pF
Note
MIN. 666 954 1600 3200 tKCY1/2 - 50 tKCY1/2 - 100 100 150 300 300 400
TYP.
MAX.
Unit ns ns ns ns ns ns ns ns ns ns ns
4.5 V VDD 5.5 V 1.8 V VDD < 4.5 V
200 300
ns ns
Note C is the load capacitance of the SCK3n and SO3n output lines. (b) 3-wire serial I/O mode (SCK3n... External clock input)
Parameter SCK3n cycle time Symbol tKCY2 Conditions 4.5 V VDD 5.5 V 3.0 V VDD < 4.5 V 2.7 V VDD < 3.0 V 1.8 V VDD < 2.7 V SCK3n high-/ low-level width tKH2, tKL2 4.5 V VDD 5.5 V 3.0 V VDD < 4.5 V 2.7 V VDD < 3.0 V 1.8 V VDD < 2.7 V SI3n setup time (to SCK3n) SI3n hold time (from SCK3n) Delay time from SCK3n to SO3n output tKSO2 tKSI2 4.5 V VDD 5.5 V 1.8 V VDD < 4.5 V C = 100 pF
Note
MIN. 666 800 1600 3200 333 400 800 1600 100
TYP.
MAX.
Unit ns ns ns ns ns ns ns ns ns
tSIK2
300 400 200 300
ns ns ns ns
4.5 V VDD 5.5 V 1.8 V VDD < 4.5 V
Note C is the load capacitance of the SO3n output line.
Remark n = 0, 1
52
Data Sheet U14042EJ4V0DS
PD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
(c) UART mode (dedicated baud-rate generator output)
Parameter Transfer rate Symbol Conditions 4.5 V VDD 5.5 V 3.0 V VDD < 4.5 V 2.7 V VDD < 3.0 V 1.8 V VDD < 2.7 V MIN. TYP. MAX. 187500 131031 78125 39063 Unit bps bps bps bps
(d) UART mode (external clock input)
Parameter ASCK0 cycle time Symbol tKCY3 Conditions 4.0 V VDD 5.5 V 2.7 V VDD < 4.0 V 1.8 V VDD < 2.7 V ASCK0 high-/low-level width tKH3, tKL3 4.0 V VDD 5.5 V 2.7 V VDD < 4.0 V 1.8 V VDD < 2.7 V Transfer rate 4.0 V VDD 5.5 V 2.7 V VDD < 4.0 V 1.8 V VDD < 2.7 V MIN. 800 1600 3200 400 800 1600 39063 19531 9766 TYP. MAX. Unit ns ns ns ns ns ns bps bps bps
(e) UART mode (infrared data transfer mode)
Parameter Transfer rate Allowable bit rate error Output pulse width Input pulse width Symbol Conditions 4.0 V VDD 5.5 V 4.0 V VDD 5.5 V 4.0 V VDD 5.5 V 4.0 V VDD 5.5 V 1.2 4/fX MIN. MAX. 131031 0.87 0.24/fbrNote Unit bps %
s s
Note fbr: Specified baud rate
Data Sheet U14042EJ4V0DS
53
PD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
A/D Converter Characteristics (TA = -40 to +85C, VDD = AVDD = 1.8 to 5.5 V, AVSS = VSS = 0 V)
Parameter Resolution Overall errorNote
Symbol
Conditions
MIN. 8
TYP. 8
MAX. 8 0.4 0.6 1.2
Unit bit %FSR %FSR %FSR
4.0 V AVREF 5.5 V 2.7 V AVREF < 4.0 V 1.8 V AVREF < 2.7 V
Conversion time
tCONV
4.5 V AVDD 5.5 V 4.0 V AVDD < 4.5 V 2.7 V AVDD < 4.0 V 1.8 V AVDD < 2.7 V
12 14 17 28 0 1.8
96 96 96 96 AVREF AVDD 40
s s s s
V V k
Analog input voltage Reference voltage Resistance between AVREF and AVSS
VIAN AVREF RREF When A/D converter not operating
20
Note Excludes quantization error (1/2 LSB). This value is indicated as a ratio (%FSR) to the full-scale value. Remark The impedance of the analog input pins is shown below. [Equivalent circuit]
R1 ANIn (n = 0 to 3) C1 C2 C3 R2
[Parameter value] (TYP.)
AVDD 2.7 V 4.5 V R1 12 k 4 k R2 8.0 k 2.7 k C1 3.0 pF 3.0 pF C2 3.0 pF 1.4 pF C3 2.0 pF 2.0 pF
Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (TA = -40 to +85C)
Parameter Data retention power supply voltage Data retention power supply current Release signal set time Oscillation stabilization time Symbol VDDDR Conditions MIN. 1.6 TYP. MAX. 5.5 Unit V
IDDDR
Subsystem clock stop (XT1 = VDD) and feed-back resistor disconnected 0 Release by RESET Release by interrupt request
0.1
30
A s
tSREL tWAIT
217/fx Note
s s
Note Selection of 212/fX and 214/fX to 217/fX is possible using bits 0 to 2 (OSTS0 to OSTS2) of the oscillation stabilization time select register (OSTS).
54
Data Sheet U14042EJ4V0DS
PD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
12.2 PD780021AY, 780022AY, 780023AY, 780024AY, and Conventional Products of PD780021A, 780022A, 780023A,780024A Absolute Maximum Ratings (TA = 25C)
Parameter Supply voltage
Symbol VDD AVDD AVREF AVSS
Conditions
Ratings -0.3 to +6.5 -0.3 to VDD + -0.3 to VDD + 0.3Note 0.3Note
Unit V V V V V
-0.3 to +0.3 P00 to P03, P10 to P17, P20 to P25, P34 to P36, P40 to P47, P50 to P57, P64 to P67, P70 to P75, X1, X2, XT1, XT2, RESET -0.3 to VDD + 0.3Note
Input voltage
VI1
VI2
P30 to P33
N-ch open-drain Without pull-up resistor With pull-up resistor
-0.3 to + 6.5 -0.3 to VDD + -0.3 to VDD + 0.3Note 0.3Note
V V V V
Output voltage Analog input voltage
VO VAN P10 to P17 Analog input pin
AVSS - 0.3 to AVREF0 + 0.3Note and -0.3 to VDD + 0.3Note -10 -15 -15 20
Output current, high
IOH
Per pin Total for P00 to P03, P40 to P47, P50 to P57, P64 to P67, P70 to P75 Total for P20 to P25, P30 to P36
mA mA mA mA
Output current, low
IOL
Per pin for P00 to P03, P20 to P25, P34 to P36, P40 to P47, P64 to P67, P70 to P75 Per pin for P30 to P33, P50 to P57 Total for P00 to P03, P40 to P47, P64 to P67, P70 to P75 Total for P20 to P25 Total for P30 to P36 Total for P50 to P57
30 50
mA mA
20 100 100 -40 to +85
mA mA mA C
Operating ambient temperature Storage temperature
TA
Tstg
-65 to +150
C
Note
6.5 V or below Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded.
Caution
Remark
Unless otherwise specified, the characteristic of alternate-function pins are the same as those of port pins.
Data Sheet U14042EJ4V0DS
55
PD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
Capacitance (TA = 25C, VDD = VSS = 0 V)
Parameter Input capacitance I/O capacitance CIO Symbol CIN f = 1 MHz Unmeasured pins returned to 0 V. f = 1 MHz Unmeasured pins returned to 0 V. P00 P34 P50 P70 to to to to P03, P20 to P25, P36, P40 to P47, P57, P64 to P67, P75 15 pF Conditions MIN. TYP. MAX. 15 Unit pF
P30 to P33
20
pF
Remark
Unless otherwise specified, the characteristic of alternate-function pins are the same as those of port pins.
Main System Clock Oscillator Characteristics (TA = -40 to +85C, VDD = 1.8 to 5.5 V)
Recommended Circuit
Resonator Ceramic resonator
Parameter Oscillation
Conditions 4.0 V VDD 5.5 V
MIN. 1.0 1.0
TYP.
MAX. 8.38 5.0 4
Unit MHz
IC
X2
X1
frequency Oscillation
(fX)Note 1
1.8 V VDD < 4.0 V After VDD reaches oscillation voltage range MIN. 4.0 V VDD 5.5 V 1.8 V VDD < 4.0 V 4.0 V VDD 5.5 V 1.8 V VDD < 4.0 V 4.0 V VDD 5.5 V
ms
C2
C1
stabilization timeNote 2 Crystal resonator
C2 C1
IC
X2
X1
Oscillation frequency (fX)Note 1 Oscillation stabilization timeNote 2
1.0 1.0
8.38 5.0 10 30
MHz ms
External clock
X2 X1
X1 input frequency X1 input high-/low-level width (tXH, tXL) (fX)Note 1
1.0 1.0 50 85
8.38 5.0 500 500
MHz ns
1.8 V VDD < 4.0 V 4.0 V VDD 5.5 V 1.8 V VDD < 4.0 V
Notes 1. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time. 2. Time required to stabilize oscillation after reset or STOP mode release. Cautions 1. When using the main system clock oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. * Keep the wiring length as short as possible. * Do not cross the wiring with the other signal lines. * Do not route the wiring near a signal line through which a high fluctuating current flows. * Always make the ground point of the oscillator capacitor the same potential as VSS1. * Do not ground the capacitor to a ground pattern through which a high current flows. * Do not fetch signals from the oscillator. 2. When the main system clock is stopped and the system is operating on the subsystem clock, wait until the oscillation stabilization time has been secured by the program before switching back to the main system clock.
56
Data Sheet U14042EJ4V0DS
PD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
Subsystem Clock Oscillator Characteristics (TA = -40 to +85C, VDD = 1.8 to 5.5 V)
Resonator Crystal resonator Recommended Circuit
XT2
R C4
Parameter Oscillation frequency (fXT)Note 1 Oscillation stabilization timeNote 2 XT1 input frequency (fXT)Note 1 XT1 input high-/low-level width (tXTH , tXTL)
Conditions
MIN. 32
TYP. 32.768
MAX. 35
Unit kHz
XT1 IC
C3
4.0 V VDD 5.5 V 1.8 V VDD < 4.0 V 32
1.2
2 10 38.5
s
External clock
kHz
XT2
XT1
12
15
s
Notes 1. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time. 2. Time required to stabilize oscillation after VDD reaches oscillation voltage range MIN. Cautions 1. When using the subsystem clock oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. * Keep the wiring length as short as possible. * Do not cross the wiring with the other signal lines. * Do not route the wiring near a signal line through which a high fluctuating current flows. * Always make the ground point of the oscillator capacitor the same potential as VSS1. * Do not ground the capacitor to a ground pattern through which a high current flows. * Do not fetch signals from the oscillator. 2. The subsystem clock oscillator is designed as a low-amplitude circuit for reducing power consumption, and is more prone to malfunction due to noise than the main system clock oscillator. Particular care is therefore required with the wiring method when the subsystem clock is used. Remark For the resonator selection and oscillator constant, customers are required to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation.
Data Sheet U14042EJ4V0DS
57
PD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
Recommended Oscillator Constant Main system clock: Ceramic resonator (TA = -40 to +85C)
Manufacturer Part Number Frequency (MHz) Murata Mfg. Co., Ltd. CSBFB1M00J58 CSBLA1M00J58 CSTCC2M00G56 CSTLS2M00G56 CSTCC3M58G53 CSTLS3M58G53 CSTCR4M00G53 CSTLS4M00G53 CSTCR4M19G53 CSTLS4M19G53 CSTCR4M91G53 CSTLS4M91G53 CSTCR5M00G53 CSTLS5M00G53 CSTCE8M00G52 CSTLS8M00G53 CSTCE8M38G52 CSTLS8M38G53 CSTCE10M0G52 CSTLS10M0G53 TDK CCR3.58MC3 CCR4.19MC3 CCR5.0MC3 CCR8.0MC5 CCR8.38MC5 1.00 1.00 2.00 2.00 3.58 3.58 4.00 4.00 4.19 4.19 4.91 4.91 5.00 5.00 8.00 8.00 8.38 8.38 10.00 10.00 3.58 4.19 5.00 8.00 8.38 Recommended Circuit Constant C1 (pF) 100 100 On-chip On-chip On-chip On-chip On-chip On-chip On-chip On-chip On-chip On-chip On-chip On-chip On-chip On-chip On-chip On-chip On-chip On-chip On-chip On-chip On-chip On-chip On-chip C2 (pF) 100 100 On-chip On-chip On-chip On-chip On-chip On-chip On-chip On-chip On-chip On-chip On-chip On-chip On-chip On-chip On-chip On-chip On-chip On-chip On-chip On-chip On-chip On-chip On-chip R1 (k) 2.2 2.2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Oscillation Voltage Range MIN. (V) 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 3.0 3.0 3.0 3.0 4.5 4.5 1.8 1.8 1.8 2.0 2.0 MAX. (V) 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5
Caution The oscillator constant is a reference value based on evaluation in specific environments by the resonator manufacturer. If the oscillator characteristics need to be optimized in the actual application, request the resonator manufacturer for evaluation on the implementation circuit. Note that the oscillation voltage and oscillation frequency merely indicate the characteristics of the oscillator. Use the internal operation conditions of the PD780024A, 780024AY Subseries within the specifications of the DC and AC characteristics.
58
Data Sheet U14042EJ4V0DS
PD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
DC Characteristics (TA = -40 to +85C, VDD = 1.8 to 5.5 V)
Parameter Output current, high Output current, low
Symbol IOH Per pin All pins IOL
Conditions
MIN.
TYP.
MAX. -1 -15 10
Unit mA mA mA
Per pin for P00 to P03, P20 to P25, P34 to P36, P40 to P47, P64 to P67, P70 to P75 Per pin for P30 to P33, P50 to P57 Total for P00 to P03, P40 to P47, P64 to P67, P70 to P75 Total for P20 to P25 Total for P30 to P36 Total for P50 to P57 2.7 V VDD 5.5 V 1.8 V VDD < 2.7 V 2.7 V VDD 5.5 V 1.8 V VDD < 2.7 V 2.7 V VDD 5.5 V 1.8 V VDD < 2.7 V 2.7 V VDD 5.5 V 1.8 V VDD < 2.7 V
15 20 10 70 70 0.7VDD 0.8VDD 0.8VDD 0.85VDD 0.7VDD 0.8VDD VDD - 0.5 VDD - 0.2 0.8VDD 0.9VDD 0 0 0 0 0 0 0 0 0 0 0 VDD - 1.0 VDD - 0.5 VDD VDD VDD VDD 5.5 5.5 VDD VDD VDD VDD 0.3VDD 0.2VDD 0.2VDD 0.15VDD 0.3VDD 0.2VDD 0.1VDD 0.4 0.2 0.2VDD 0.1VDD VDD VDD 2.0 0.4 2.0 0.4
mA mA mA mA mA V V V V V V V V V V V V V V V V V V V V V V V V V V
Input voltage, high
VIH1
P10 to P17, P21, P24, P35, P40 to P47, P50 to P57, P64 to P67, P74, P75
VIH2
P00 to P03, P20, P22, P23, P25, P34, P36, P70 to P73, RESET
VIH3
P30 to P33 (N-ch open-drain)
VIH4
X1, X2
VIH5
XT1, XT2
4.0 V VDD 5.5 V 1.8 V VDD < 4.0 V
Input voltage, low
VIL1
P10 to P17, P21, P24, P35, P40 to P47, P50 to P57, P64 to P67, P74, P75
2.7 V VDD 5.5 V 1.8 V VDD < 2.7 V 2.7 V VDD 5.5 V 1.8 V VDD < 2.7 V 4.0 V VDD 5.5 V 2.7 V VDD < 4.0 V 1.8 V VDD < 2.7 V 2.7 V VDD 5.5 V 1.8 V VDD < 2.7 V 4.0 V VDD 5.5 V 1.8 V VDD < 4.0 V
VIL2
P00 to P03, P20, P22, P23, P25, P34, P36, P70 to P73, RESET
VIL3
P30 to P33
VIL4
X1, X2
VIL5
XT1, XT2
Output voltage, high Output voltage, low
VOH1
4.0 V VDD 5.5 V, IOH = -1 mA 1.8 V VDD < 4.0 V, IOH = -100 A 4.0 V VDD 5.5 V, IOL = 15 mA
VOL1
P30 to P33 P50 to P57
P00 to P03, P20 to P25, P34 to P36, 4.0 V VDD 5.5 V, P40 to P47, P64 to P67, P70 to P75 VOL2 IOL = 400 A IOL = 1.6 mA
0.5
V
Remark
Unless otherwise specified, the characteristics of alternate-function pins are the same as those of port pins.
Data Sheet U14042EJ4V0DS
59
PD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
DC Characteristics (TA = -40 to +85C, VDD = 1.8 to 5.5 V)
Parameter Input leakage current, high Symbol ILIH1 VIN = VDD Conditions P00 to P03, P10 to P17, P20 to P25, P34 to P36, P40 to P47, P50 to P57, P60 to P67, P70 to P75, RESET X1, X2, XT1, XT2 VIN = 5.5 V VIN = 0 V P30 to P33Note 1 P00 to P03, P10 to P17, P20 to P25, P34 to P36, P40 to P47, P50 to P57, P64 to P67, P70 to P75, RESET X1, X2, XT1, XT2 P30 to VOUT = VDD VOUT = 0 V VIN = 0 V, P30, P31, P32Note 2, P33Note 2 VIN = 0 V, P00 to P03, P20 to P25, P34 to P36, P40 to P47, P50 to P57, P64 to P67, P70 to P75 15 15 30 30 P33Note 1 MIN. TYP. MAX. 3 Unit
A
ILIH2 ILIH3 Input leakage current, low ILIL1
20 3 -3
A A A
ILIL2 ILIL3 Output leakage current, high Output leakage current, low Mask option pull-up resistance Software pullup resistance ILOH ILOL R1 R2
-20 -3 3 -3 90 90
A A A A
k k
Notes 1. PD780021A, 780022A, 780023A, 780024A: When pull-up resistors are not connected to P30 to P33 (specified by the mask option).
PD780021AY, 780022AY, 780023AY, 780024AY: When pull-up resistors are not connected to P30
and P31 (specified by the mask option). 2. Only for the PD780021A, 780022A, 780023A, and 780024A. Remark Unless otherwise specified, the characteristics of alternate-function pins are the same as those of port pins.
60
Data Sheet U14042EJ4V0DS
PD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
DC Characteristics (TA = -40 to +85C, VDD = 1.8 to 5.5 V)
Parameter Power supply currentNote 1 Symbol Conditions IDD1Note 2 8.38 MHz VDD = 5.0 V 10%Note 3 crystal oscillation operating mode 5.00 MHz VDD = 3.0 V 10%Note 3 crystal oscillation operating mode VDD = 2.0 V 10%Note 4 MIN. When A/D converter is stopped When A/D converter is operatingNote 6 When A/D converter is stopped When A/D converter is operatingNote 6 When A/D converter is stopped When A/D converter is operatingNote 6 IDD2 8.38 MHz VDD = 5.0 V 10%Note 3 crystal oscillation HALT mode 5.00 MHz crystal oscillation HALT mode VDD = 2.0 V 10%Note 4 VDD = 3.0 V 10%Note 3 When peripheral functions are stopped When peripheral functions are operating When peripheral functions are stopped When peripheral functions are operating When peripheral functions are stopped When peripheral functions are operating
IDD3
TYP. 5.5 6.5 2 3 0.4 1.4 1.1
MAX. 11 13 4 6 1.5 4.2 2.2 4.7
Unit mA mA mA mA mA mA mA mA mA mA mA mA
0.35
0.7 1.7
0.15
0.4 1.1
32.768 kHz crystal oscillation operating modeNote 5
VDD = 5.0 V 10% VDD = 3.0 V 10% VDD = 2.0 V 10% VDD = 5.0 V 10% VDD = 3.0 V 10% VDD = 2.0 V 10% VDD = 5.0 V 10% VDD = 3.0 V 10% VDD = 2.0 V 10%
40 20 10 30 6 2 0.1 0.05 0.05
80 40 20 60 18 10 30 10 10
A A A A A A A A A
IDD4
32.768 kHz crystal oscillation HALT modeNote 5
IDD5
XT1 = VDD STOP mode When feedback resistor is not used
Notes 1. Total current through the internal power supply (VDD0, VDD1) (except the current through pull-up resistors of ports). 2. IDD1 includes the peripheral operation current. 3. When the processor clock control register (PCC) is set to 00H. 4. When PCC is set to 02H. 5. When main system clock operation is stopped. 6. Includes the current through the AVDD pin.
Data Sheet U14042EJ4V0DS
61
PD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
AC Characteristics (1) Basic Operation (TA = -40 to +85C, VDD = 1.8 to 5.5 V)
Parameter Cycle time (Min. instruction execution time) Symbol TCY Operating with main system clock Conditions 4.0 V VDD 5.5 V 2.7 V VDD < 4.0 V 1.8 V VDD < 2.7 V Operating with subsystem clock TI00, TI01 input high-/low-level width TI50, TI51 input frequency TI50, TI51 input high-/low-level width Interrupt request input high-/lowlevel width RESET low-level width tRSL tINTH, tINTL tTIH5, tTIL5 fTI5 tTIH0, tTIL0 4.0 V VDD 5.5 V 2.7 V VDD < 4.0 V 1.8 V VDD < 2.7 V 2.7 V VDD 5.5 V 1.8 V VDD < 2.7 V 2.7 V VDD 5.5 V 1.8 V VDD < 2.7 V INTP0 to INTP3, P40 to P47 2.7 V VDD 5.5 V 1.8 V VDD < 2.7 V 2.7 V VDD 5.5 V 1.8 V VDD < 2.7 V MIN. 0.238 0.4 1.6 103.9Note 1 2/fsam+0.1Note 2 2/fsam+0.2Note 2 2/fsam+0.5Note 2 0 0 100 1.8 1 2 10 20 4 275 122 TYP. MAX. 16 16 16 125 Unit
s s s s s s s
MHz kHz ns ns
s s s s
Notes 1. Value when the external clock is used. When a crystal resonator is used, it is 114 s (MIN.). 2. Selection of fsam = fX, fX/4, fX/64 is possible using bits 0 and 1 (PRM00, PRM01) of prescaler mode register 0 (PRM0). However, if the TI00 valid edge is selected as the count clock, the value becomes fsam = fX/8.
62
Data Sheet U14042EJ4V0DS
PD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
TCY vs. VDD (main system clock operation)
16.0 10.0
Cycle time TCY [ S]
5.0
Operation guaranteed range
2.0 1.6 1.0
0.4 0.238 0.1 0 1.0 1.8 2.0 2.7 Supply voltage VDD [V] 3.0 4.0 5.0 5.5 6.0
Data Sheet U14042EJ4V0DS
63
PD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
(2) Read/Write Operation (TA = -40 to +85C, VDD = 4.0 to 5.5 V)
Parameter ASTB high-level width Address setup time Address hold time Data input time from address Symbol tASTH tADS tADH tADD1 tADD2 Address output time from RD Data input time from RD tRDAD tRDD1 tRDD2 Read data hold time RD low-level width tRDH tRDL1 tRDL2 Input time from RD to WAIT tRDWT1 tRDWT2 Input time from WR to WAIT WAIT low-level width Write data setup time Write data hold time WR low-level width Delay time from ASTB to RD Delay time from ASTB to WR Delay time from RD to ASTB at external fetch Address hold time from RD at external fetch Write data output time from RD Write data output time from WR Address hold time from WR Delay time from WAIT to RD Delay time from WAIT to WR tRDWD tWRWD tWRADH tWTRD tWTWR 40 10 0.8tCY - 15 0.8tCY 0.8tCY 60 1.2tCY + 30 2.5tCY + 25 2.5tCY + 25 tRDADH 0.8tCY - 15 1.2tCY + 30 tWRWT tWTL tWDS tWDH tWRL1 tASTRD tASTWR tRDAST (0.5 + n)tCY + 10 60 6 (1.5 + 2n)tCY - 15 6 2tCY - 15 0.8tCY - 15 1.2tCY 0 (1.5 + 2n)tCY - 33 (2.5 + 2n)tCY - 33 tCY - 43 tCY - 43 tCY - 25 (2 + 2n)tCY 0 Conditions MIN. 0.3tCY 20 6 (2 + 2n)tCY - 54 (3 + 2n)tCY - 60 100 (2 + 2n)tCY - 87 (3 + 2n)tCY - 93 MAX.
(1/3)
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
ns
ns ns ns ns ns
Caution Remarks
TCY can only be used when the MIN. value is 0.238 s. 1. 2. 3. tCY = TCY/4 n indicates the number of waits. CL = 100 pF (CL indicates the load capacitance of the AD0 to AD7, A8 to A15, RD, WR, WAIT, and ASTB pins.)
64
Data Sheet U14042EJ4V0DS
PD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
(2) Read/Write Operation (TA = -40 to +85C, VDD = 2.7 to 4.0 V) (2/3)
Parameter ASTB high-level width Address setup time Address hold time Input time from address to data Symbol tASTH tADS tADH tADD1 tADD2 Output time from RD to address Input time from RD to data tRDAD tRDD1 tRDD2 Read data hold time RD low-level width tRDH tRDL1 tRDL2 Input time from RD to WAIT tRDWT1 tRDWT2 Input time from WR to WAIT WAIT low-level width Write data setup time Write data hold time WR low-level width Delay time from ASTB to RD Delay time from ASTB to WR Delay time from RD to ASTB at external fetch Hold time from RD to address at external fetch Write data output time from RD Write data output time from WR Hold time from WR to address Delay time from WAIT to RD Delay time from WAIT to WR tRDWD tWRWD tWRADH tWTRD tWTWR 40 20 0.8tCY - 30 0.5tCY 0.5tCY 120 1.2tCY + 60 2.5tCY + 50 2.5tCY + 50 ns ns ns ns ns tRDADH 0.8tCY - 30 1.2tCY + 60 ns tWRWT tWTL tWDS tWDH tWRL1 tASTRD tASTWR tRDAST (0.5 + 2n)tCY + 10 60 10 (1.5 + 2n)tCY - 30 10 2tCY - 30 0.8tCY - 30 1.2tCY 0 (1.5 + 2n)tCY - 40 (2.5 + 2n)tCY - 40 tCY - 75 tCY - 60 tCY - 50 (2 + 2n)tCY 0 Conditions MIN. 0.3tCY 30 10 (2 + 2n)tCY - 108 (3 + 2n)tCY - 120 200 (2 + 2n)tCY - 148 (3 + 2n)tCY - 162 MAX. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Caution Remarks
TCY can only be used when the MIN. value is 0.4 s. 1. 2. 3. tCY = TCY/4 n indicates the number of waits. CL = 100 pF (CL indicates the load capacitance of the AD0 to AD7, AD8 to AD15, RD, WR, WAIT, and ASTB pins.)
Data Sheet U14042EJ4V0DS
65
PD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
(2) Read/Write Operation (TA = -40 to +85C, VDD = 1.8 to 2.7 V) (3/3)
Parameter ASTB high-level width Address setup time Address hold time Input time from address to data Symbol tASTH tADS tADH tADD1 tADD2 Output time from RD to address Input time from RD to data tRDAD tRDD1 tRDD2 Read data hold time RD low-level width tRDH tRDL1 tRDL2 Input time from RD to WAIT tRDWT1 tRDWT2 Input time from WR to WAIT WAIT low-level width Write data setup time Write data hold time WR low-level width Delay time from ASTB to RD Delay time from ASTB to WR Delay time from RD to ASTB at external fetch Hold time from RD to address at external fetch Write data output time from RD Write data output time from WR Hold time from WR to address Delay time from WAIT to RD Delay time from WAIT to WR tRDWD tWRWD tWRADH tWTRD tWTWR 40 40 0.8tCY - 60 0.5tCY 0.5tCY 240 1.2tCY + 120 2.5tCY + 100 2.5tCY + 100 ns ns ns ns ns tRDADH 0.8tCY - 60 1.2tCY + 120 ns tWRWT tWTL tWDS tWDH tWRL1 tASTRD tASTWR tRDAST (0.5 + 2n)tCY + 10 60 20 (1.5 + 2n)tCY - 60 20 2tCY - 60 0.8tCY - 60 1.2tCY 0 (1.5 + 2n)tCY - 92 (2.5 + 2n)tCY - 92 tCY - 350 tCY - 132 tCY - 100 (2 + 2n)tCY 0 Conditions MIN. 0.3tCY 120 20 (2 + 2n)tCY - 233 (3 + 2n)tCY - 240 400 (2 + 2n)tCY - 325 (3 + 2n)tCY - 332 MAX. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Caution Remarks
TCY can only be used when the MIN. value is 1.6 s. 1. 2. 3. tCY = TCY/4 n indicates the number of waits. CL = 100 pF (CL indicates the load capacitance of the AD0 to AD7, AD8 to AD15, RD, WR, WAIT, and ASTB pins.)
66
Data Sheet U14042EJ4V0DS
PD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
(3) Serial Interface (TA = -40 to +85C, VDD = 1.8 to 5.5 V) (a) 3-wire serial I/O mode (SCK3n... Internal clock output)
Parameter SCK3n cycle time Symbol tKCY1 Conditions 4.0 V VDD 5.5 V 2.7 V VDD < 4.0 V 1.8 V VDD < 2.7 V SCK3n high-/ low-level width SI3n setup time (to SCK3n) tSIK1 tKH1, tKL1 4.0 V VDD 5.5 V 1.8 V VDD < 4.0 V 4.0 V VDD 5.5 V 2.7 V VDD < 4.0 V 1.8 V VDD < 2.7 V SI3n hold time (from SCK3n) Delay time from SCK3n to SO3n output tKSO1 C = 100 pF
Note
MIN. 954 1600 3200 tKCY1/2 - 50 tKCY1/2 - 100 100 150 300 400
TYP.
MAX.
Unit ns ns ns ns ns ns ns ns ns
tKSI1
300
ns
Note C is the load capacitance of the SCK3n and SO3n output lines. (b) 3-wire serial I/O mode (SCK3n... External clock input)
Parameter SCK3n cycle time Symbol tKCY2 Conditions 4.0 V VDD 5.5 V 2.7 V VDD < 4.0 V 1.8 V VDD < 2.7 V SCK3n high-/ low-level width tKH2, tKL2 4.0 V VDD 5.5 V 2.7 V VDD < 4.0 V 1.8 V VDD < 2.7 V SI3n setup time (to SCK3n) SI3n hold time (from SCK3n) Delay time from SCK3n to SO3n output tKSO2 C = 100 pF
Note
MIN. 800 1600 3200 400 800 1600 100
TYP.
MAX.
Unit ns ns ns ns ns ns ns
tSIK2
tKSI2
400
ns
300
ns
Note C is the load capacitance of the SO3n output line. Remark Conventional products of PD780021A, 780022A, 780023A, 780024A: n = 0 or 1
PD780021AY, 780022AY, 780023AY, 780024AY: n = 0
Data Sheet U14042EJ4V0DS
67
PD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
(c) UART mode (dedicated baud-rate generator output)
Parameter Transfer rate Symbol Conditions 4.0 V VDD 5.5 V 2.7 V VDD < 4.0 V 1.8 V VDD < 2.7 V MIN. TYP. MAX. 131031 78125 39063 Unit bps bps bps
(d) UART mode (external clock input)
Parameter ASCK0 cycle time Symbol tKCY3 Conditions 4.0 V VDD 5.5 V 2.7 V VDD < 4.0 V 1.8 V VDD < 2.7 V ASCK0 high-/low-level width tKH3, tKL3 4.0 V VDD 5.5 V 2.7 V VDD < 4.0 V 1.8 V VDD < 2.7 V Transfer rate 4.0 V VDD 5.5 V 2.7 V VDD < 4.0 V 1.8 V VDD < 2.7 V MIN. 800 1600 3200 400 800 1600 39063 19531 9766 TYP. MAX. Unit ns ns ns ns ns ns bps bps bps
(e) UART mode (infrared data transfer mode)
Parameter Transfer rate Allowable bit rate error Output pulse width Input pulse width Symbol Conditions 4.0 V VDD 5.5 V 4.0 V VDD 5.5 V 4.0 V VDD 5.5 V 4.0 V VDD 5.5 V 1.2 4/fX MIN. MAX. 131031 0.87 0.24/fbrNote Unit bps %
s s
Note
fbr: Specified baud rate
68
Data Sheet U14042EJ4V0DS
PD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
(f) I2C bus mode (PD780021AY, 780022AY, 780023AY, 780024AY only)
Parameter SCL0 clock frequency Bus free time (between stop and start conditions) Hold timeNote 1 SCL0 clock low-level width SCL0 clock high-level width Start/restart condition setup time Data hold time CBUS-compatible master I2C bus Data setup time SDA0 and SCL0 signal rise time SDA0 and SCL0 signal fall time Stop condition setup time Spike pulse width controlled by input filter Capacitive load per bus line tSU:DAT tR tF tSU:STO tSP Cb tHD:STA tLOW tHIGH tSU:STA tHD:DAT 4.0 4.7 4.0 4.7 5.0 0Note 2 250 -- -- 4.0 -- -- -- -- -- -- -- -- -- 1000 300 -- -- 400 0.6 1.3 0.6 0.6 -- 0Note 2 100Note 4 20 + 0.1CbNote 5 20 + 0.1CbNote 5 0.6 0 -- -- -- -- -- -- 0.9 Note 3 -- 300 300 -- 50 400 Symbol fCLK tBUF Standard Mode MIN. MAX. 0 4.7 100 -- High-Speed Mode MIN. MAX. 0 1.3 400 -- Unit kHZ
s s s s s s s
ns ns ns
s
ns pF
Notes 1. In the start condition, the first clock pulse is generated after this hold time. 2. To fill in the undefined area of the SCL0 falling edge, it is necessary for the device to internally provide at least 300 ns of hold time for the SDA0 signal (which is VIHmin. of the SCL0 signal). 3. If the device does not extend the SCL0 signal low hold time (tLOW), only the maximum data hold time tHD:DAT needs to be fulfilled. 4. The high-speed mode I2C bus is available in a standard mode I2C bus system. At this time, the conditions described below must be satisfied. * If the device does not extend the SCL0 signal low state hold time tSU:DAT 250 ns * If the device extends the SCL0 signal low state hold time Be sure to transmit the next data bit to the SDA0 line before the SCL0 line is released (tRmax. + tSU:DAT = 1000 + 250 = 1250 ns by standard mode I2C bus specification). 5. Cb: Total capacitance per bus line (unit: pF)
Data Sheet U14042EJ4V0DS
69
PD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
A/D Converter Characteristics (TA = -40 to +85C, VDD = AVDD = 1.8 to 5.5 V, AVSS = VSS = 0 V)
Parameter Resolution Overall errorNote 4.0 V AVREF 5.5 V 2.7 V AVREF < 4.0 V 1.8 V AVREF < 2.7 V Conversion time tCONV 4.0 V AVDD 5.5 V 2.7 V AVDD < 4.0 V 1.8 V AVDD < 2.7 V Analog input voltage Reference voltage Resistance between AVREF and AVSS VIAN AVREF RREF When A/D converter not operating 14 19 28 0 1.8 20 40 Symbol Conditions MIN. 8 TYP. 8 MAX. 8 0.4 0.6 1.2 96 96 96 AVREF AVDD Unit bit %FSR %FSR %FSR
s s s
V V k
Note Excludes quantization error (1/2 LSB). This value is indicated as a ratio (%FSR) to the full-scale value. Remark The impedance of the analog input pins is shown below. [Equivalent circuit]
R1 ANIn (n = 0 to 3) C1 C2 C3 R2
[Parameter value] (TYP.)
AVDD 2.7 V 4.5 V R1 12 k 4 k R2 8.0 k 2.7 k C1 3.0 pF 3.0 pF C2 3.0 pF 1.4 pF C3 2.0 pF 2.0 pF
Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (TA = -40 to +85C)
Parameter Data retention power supply voltage Data retention power supply current Release signal set time Oscillation stabilization time Symbol VDDDR Conditions MIN. 1.6 TYP. MAX. 5.5 Unit V
IDDDR
Subsystem clock stop (XT1 = VDD) and feed-back resistor disconnected 0 Release by RESET Release by interrupt request
0.1
30
A s
tSREL tWAIT
217/fx Note
s s
Note Selection of 212/fX and 214/fX to 217/fX is possible using bits 0 to 2 (OSTS0 to OSTS2) of the oscillation stabilization time select register (OSTS).
70
Data Sheet U14042EJ4V0DS
PD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
12.3 Timing Chart
AC Timing Test Points (excluding X1, XT1 inputs)
0.8VDD 0.2VDD
Point of measurement
0.8VDD 0.2VDD
Clock Timing
1/fX
tXL
tXH VIH4 (MIN.) VIL4 (MAX.)
X1 input
1/fXT
tXTL XT1 input
tXTH VIH5 (MIN.) VIL5 (MAX.)
TI Timing
tTIL0 tTIH0
TI00, TI01
1/fT5 tTIL5 tTIH5
TI50, TI51
Data Sheet U14042EJ4V0DS
71
PD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
Interrupt Request Input Timing
tINTL
tINTH
INTP0 to INTP3
RESET Input Timing
tRSL
RESET
72
Data Sheet U14042EJ4V0DS
PD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
Read/Write Operation External fetch (no wait):
A8 to A15
Higher 8-bit address tADD1
AD0 to AD7
Lower 8-bit address tADS tASTH tADH
Hi-Z tRDAD tRDD1
Instruction code tRDADH tRDAST
ASTB
RD tASTRD tRDL1 tRDH
External fetch (wait insertion):
A8 to A15
Higher 8-bit address tADD1
AD0 to AD7
Lower 8-bit address tADS tASTH tADH tRDAD
Hi-Z tRDD1
Instruction code tRDADH tRDAST
ASTB
RD tASTRD WAIT tRDWT1 tWTL tWTRD tRDL1 tRDH
Data Sheet U14042EJ4V0DS
73
PD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
External data access (no wait):
A8 to A15 tADD2 AD0 to AD7 Lower 8-bit address tADS tASTH ASTB tADH Hi-Z tRDAD tRDD2
Higher 8-bit address
Read Data
Write data
Hi-Z
tRDH
RD tASTRD WR tASTWR tWRL1 tRDL2 tRDWD tWRWD tWDS tWDH tWRADH
External data access (wait insertion):
A8 to A15 tADD2 AD0 to AD7
Lower 8-bit address
Higher 8-bit address
Hi-Z Hi-Z
Read data
tRDH
Write data
tADS tADH tASTH ASTB
tRDAD tRDD2 tASTRD
RD
tRDL2
tRDWD tWRWD
tWDS
tWDH
WR
tASTWR WAIT tRDWT2 tWTL tWTRD tWRWT tWTL tWTWR tWRL1 tWRADH
74
Data Sheet U14042EJ4V0DS
PD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
Serial Transfer Timing 3-wire serial I/O mode:
tKCYm tKLm tKHm
SCK3n
tSIKm
tKSIm
SI3n
tKSOm
Input data
SO3n
Output data
Remarks 1. m = 1, 2 2. PD780021A, 780022A, 780023A, 780024A: n = 0, 1
PD780021AY, 780022AY, 780023AY, 780024AY: n = 0
UART mode (external clock input):
tKCY3 t KL3 tKH3
ASCK0
I2C bus mode (PD780021AY, 780022AY, 780023AY, 780024AY only):
tLOW SCL0 tHD:DAT tHD:STA tHIGH tSU:DAT tF tSU:STA tHD:STA tSP tSU:STO
tR
SDA0 tBUF Stop condition Start condition Restart condition Stop condition
Data Sheet U14042EJ4V0DS
75
PD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
Data Retention Timing (STOP Mode Release by RESET)
Internal reset operation HALT mode STOP mode Operating mode
Data retention mode
VDD
STOP instruction execution
VDDDR
tSREL
RESET
tWAIT
Data Retention Timing (Standby Release Signal: STOP Mode Release by Interrupt Request Signal)
HALT mode STOP mode Operating mode
Data retention mode
VDD STOP Instruction execution Standby release signal (interrupt request)
VDDDR tSREL
tWAIT
76
Data Sheet U14042EJ4V0DS
PD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
13. PACKAGE DRAWINGS
64-PIN PLASTIC SDIP (19.05mm(750))
64 33
1 A
32
K J I L
F D H G N
M
M C B
R
NOTES 1. Each lead centerline is located within 0.17 mm of its true position (T.P.) at maximum material condition. 2. Item "K" to center of leads when formed parallel.
ITEM A B C D F G H I J K L M N R
MILLIMETERS 58.0+0.68 -0.20 1.78 MAX. 1.778 (T.P.) 0.500.10 0.9 MIN. 3.20.3 0.51 MIN. 4.05+0.26 -0.20 5.08 MAX. 19.05 (T.P.) 17.00.2 0.25+0.10 -0.05 0.17 0 ~ 15 P64C-70-750A,C-4
Remark The external dimensions and materials of the ES version are the same as those of the mass-produced version.
Data Sheet U14042EJ4V0DS
77
PD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
64-PIN PLASTIC QFP (14x14)
A B
48 49
33 32
detail of lead end
S CD Q R
64 1
17 16
F G
H
J I
M
P
K
S
N
S
L M
ITEM A B
C
NOTE Each lead centerline is located within 0.15 mm of its true position (T.P.) at maximum material condition.
MILLIMETERS 17.60.4 14.00.2
14.00.2
D
F
17.60.4
1.0
G
H
1.0
0.37 +0.08 -0.07
I J
0.15 0.8 (T.P.) 1.80.2
0.80.2
0.17 +0.08 -0.07
K
L
M
N P Q
R S
0.10 2.550.1 0.10.1
5 5 2.85 MAX.
P64GC-80-AB8-5
Remark The external dimensions and materials of the ES version are the same as those of the mass-produced version.
78
Data Sheet U14042EJ4V0DS
PD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
64-PIN PLASTIC LQFP (14x14)
A B
48 49
33 32
detail of lead end S P C D
T
R 64 1 F G H I
M
L U
17 16 Q
J
ITEM A B
MILLIMETERS 17.20.2 14.00.2 14.00.2 17.20.2 1.0 1.0 0.37 +0.08 -0.07 0.20 0.8 (T.P.) 1.60.2 0.8 0.17 +0.03 -0.06 0.10 1.40.1 0.1270.075 +4 3 -3 1.7 MAX. 0.25 0.8860.15 P64GC-80-8BS
K S
C D F G H
N
S
M
I J K
NOTE Each lead centerline is located within 0.20 mm of its true position (T.P.) at maximum material condition.
L M N P Q R S T U
Remark The external dimensions and materials of the ES version are the same as those of the mass-produced version.
Data Sheet U14042EJ4V0DS
79
PD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
64-PIN PLASTIC TQFP (12x12)
A B
48 49
33 32 S P
detail of lead end
T C D R
L U
64 1 F G H I
M
17 16
Q
J
ITEM A B C D F MILLIMETERS 14.00.2 12.00.2 12.00.2 14.00.2 1.125 1.125 0.32 +0.06 -0.10 0.13 0.65 (T.P.) 1.00.2 0.5 0.17 +0.03 -0.07 0.10 1.0 0.10.05 3 +4 -3 1.10.1 0.25 0.60.15 P64GK-65-9ET-3
K S M N
NOTE Each lead centerline is located within 0.13 mm of its true position (T.P.) at maximum material condition.
G H I J K L M N P Q R S T U
S
Remark The external dimensions and materials of the ES version are the same as those of the mass-produced version.
80
Data Sheet U14042EJ4V0DS
PD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
64-PIN PLASTIC LQFP (10x10)
A B
48 49
33 32 S P
detail of lead end
C
D
T
R 64 1 F G H I
M
L U
17 16
Q
J
K S
ITEM A B C D F G H I J K L M N P Q R S T U
MILLIMETERS 12.00.2 10.00.2 10.00.2 12.00.2 1.25 1.25 0.220.05 0.08 0.5 (T.P.) 1.00.2 0.5 0.17 +0.03 -0.07 0.08 1.4 0.10.05 3 +4 -3 1.50.10 0.25 0.60.15 S64GB-50-8EU-1
N
S
M
Remark The external dimensions and materials of the ES version are the same as those of the mass-produced version.
Data Sheet U14042EJ4V0DS
81
PD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
73-PIN PLASTIC FBGA (9x9)
D
wSA
ZE
ZD
A
B E
9 8 7 6 5 4 3 2 1 JHGFEDCBA
INDEX MARK
wSB
A y1 S A2
(UNIT:mm)
S
ITEM D E w
DIMENSIONS 9.000.10 9.000.10 0.20 1.280.10 0.350.06 0.93 0.80 0.50 +0.05 -0.10 0.08 0.10 0.20 1.30 1.30 P73F1-80-CN3
y
S
e
A1
A A1 A2 e b x y y1 ZD ZE
b
x
M
S AB
Remark The external dimensions and materials of the ES version are the same as those of the mass-produced version.
82
Data Sheet U14042EJ4V0DS
PD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
14. RECOMMENDED SOLDERING CONDITIONS
This product should be soldered and mounted under the following recommended conditions. For details of the recommended soldering conditions, refer to the document Semiconductor Device Mounting Technology Manual (C10535E). For soldering methods and conditions other than those recommended below, contact an NEC Electronics sales representative. Table 14-1. Surface Mounting Type Soldering Conditions (1/3) xxx (1) PD780021AGC-xxx xxx-AB8: 64-pin plastic QFP (14 x 14) xxx-AB8: 64-pin plastic QFP (14 x 14) PD780022AGC-xxx xxx xxx-AB8: 64-pin plastic QFP (14 x 14) PD780023AGC-xxx xxx xxx-AB8: 64-pin plastic QFP (14 x 14) PD780024AGC-xxx xxx xxx-AB8: 64-pin plastic QFP (14 x 14) PD780021AYGC-xxx xxx xxx-AB8: 64-pin plastic QFP (14 x 14) PD780022AYGC-xxx xxx xxx-AB8: 64-pin plastic QFP (14 x 14) PD780023AYGC-xxx xxx xxx xxx-AB8: 64-pin plastic QFP (14 x 14) PD780024AYGC-xxx
Soldering Method Infrared reflow Soldering Conditions Package peak temperature: 235C, Time: 30 seconds max. (at 210C or higher), Count: Three times or less VPS Package peak temperature: 215C, Time: 40 seconds max. (at 200C or higher), Count: Three times or less Wave soldering Solder bath temperature: 260C max., Time: 10 seconds max., Count: Once, Preheating temperature: 120C Max. (package surface temperature) Partial heating Pin temperature: 300C max., Time: 3 seconds max. (per pin row) - WS60-00-1 VP15-00-3 Recommended Condition Symbol IR35-00-3
Caution Do not use different soldering methods together (except for partial heating). (2) PD780021AGC-xxx xxx-8BS: 64-pin plastic LQFP (14 x 14) xxx xxx-8BS: 64-pin plastic LQFP (14 x 14) xxx PD780022AGC-xxx xxx-8BS: 64-pin plastic LQFP (14 x 14) PD780023AGC-xxx xxx xxx-8BS: 64-pin plastic LQFP (14 x 14) PD780024AGC-xxx xxx xxx-8BS: 64-pin plastic LQFP (14 x 14) xxx PD780021AYGC-xxx xxx-8BS: 64-pin plastic LQFP (14 x 14) PD780022AYGC-xxx xxx xxx-8BS: 64-pin plastic LQFP (14 x 14) PD780023AYGC-xxx xxx xxx xxx-8BS: 64-pin plastic LQFP (14 x 14) PD780024AYGC-xxx
Soldering Method Infrared reflow Soldering Conditions Package peak temperature: 235C, Time: 30 seconds max. (at 210C or higher), Count: Two times or less VPS Package peak temperature: 215C, Time: 40 seconds max. (at 200C or higher), Count: Two times or less Wave soldering Solder bath temperature: 260C max., Time: 10 seconds max., Count: Once, Preheating temperature: 120C Max. (package surface temperature) Partial heating Pin temperature: 300C max., Time: 3 seconds max. (per pin row) - WS60-00-1 VP15-00-2 Recommended Condition Symbol IR35-00-2
Caution Do not use different soldering methods together (except for partial heating).
Data Sheet U14042EJ4V0DS
83
PD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
Table 14-1. Surface Mounting Type Soldering Conditions (2/3) xxx-9ET: 64-pin plastic TQFP (12 x 12) (3) PD780021AGK-xxx xxx xxx xxx-9ET: 64-pin plastic TQFP (12 x 12) PD780022AGK-xxx xxx xxx-9ET: 64-pin plastic TQFP (12 x 12) PD780023AGK-xxx xxx-9ET: 64-pin plastic TQFP (12 x 12) xxx PD780024AGK-xxx xxx xxx-9ET: 64-pin plastic TQFP (12 x 12) PD780021AYGK-xxx xxx xxx-9ET: 64-pin plastic TQFP (12 x 12) PD780022AYGK-xxx xxx-9ET: 64-pin plastic TQFP (12 x 12) PD780023AYGK-xxx xxx xxx PD780024AYGK-xxx xxx-9ET: 64-pin plastic TQFP (12 x 12)
Recommended Condition Symbol IR35-107-2
Soldering Method Infrared reflow
Soldering Conditions Package peak temperature: 235C, Time: 30 seconds max. (at 210C or higher), Count: Two times or less, Exposure limit: 7 daysNote (after that, prebake at 125C for 10 hours)
VPS
Package peak temperature: 215C, Time: 40 seconds max. (at 200C or higher), Count: Two times or less, Exposure limit: 7 daysNote (after that, prebake at 125C for 10 hours)
VP15-107-2
Wave soldering
Solder bath temperature: 260C max., Time: 10 seconds max., Count: Once, Preheating temperature: 120C Max. (package surface temperature), Exposure limit: 7 daysNote (after that, prebake at 125C for 10 hours)
WS60-107-1
Partial heating
Pin temperature: 300C max., Time: 3 seconds max. (per pin row)
--
Note
After opening the dry pack, store it at 25C or less and 65%RH or less for the allowable storage period.
Caution Do not use different soldering methods together (except for partial heating).
84
Data Sheet U14042EJ4V0DS
PD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
Table 14-1. Surface Mounting Type Soldering Conditions (3/3) xxx xxx-8EU: 64-pin plastic LQFP (10 x 10) (4) PD780021AGB-xxx xxx xxx-8EU: 64-pin plastic LQFP (10 x 10) PD780022AGB-xxx PD780023AGB-xxx xxx xxx-8EU: 64-pin plastic LQFP (10 x 10) xxx-8EU: 64-pin plastic LQFP (10 x 10) PD780024AGB-xxx xxx
PD780021AYGB-xxx xxx xxx-8EU: 64-pin plastic LQFP (10 x 10) xxx-8EU: 64-pin plastic LQFP (10 x 10) PD780022AYGB-xxx xxx PD780023AYGB-xxx xxx xxx-8EU: 64-pin plastic LQFP (10 x 10)
xxx-8EU: 64-pin plastic LQFP (10 x 10) PD780024AYGB-xxx xxx
Recommended Condition Symbol IR35-00-2
Soldering Method Infrared reflow
Soldering Conditions Package peak temperature: 235C, Time: 30 seconds max. (at 210C or higher), Count: Twice or less
VPS
Package peak temperature: 215C, Time: 40 seconds max. (at 200C or higher), Count: Twice or less
VP15-00-2
Partial heating
Pin temperature: 300C max., Time: 3 seconds max. (per pin row)
--
Caution Do not use different soldering methods together (except for partial heating). xxx-CN3: 73-pin plastic FBGA (9 x 9) (5) PD780021AF1-xxx xxx xxx xxx-CN3: 73-pin plastic FBGA (9 x 9) PD780022AF1-xxx xxx-CN3: 73-pin plastic FBGA (9 x 9) PD780023AF1-xxx xxx xxx xxx-CN3: 73-pin plastic FBGA (9 x 9) PD780024AF1-xxx xxx xxx-CN3: 73-pin plastic FBGA (9 x 9) PD780021AYF1-xxx PD780022AYF1-xxx xxx-CN3: 73-pin plastic FBGA (9 x 9) xxx xxx PD780023AYF1-xxx xxx-CN3: 73-pin plastic FBGA (9 x 9) xxx PD780024AYF1-xxx xxx-CN3: 73-pin plastic FBGA (9 x 9)
Recommended Condition Symbol IR60-203-3
Soldering Method Infrared reflow
Soldering Conditions Package peak temperature: 260C, Time: 60 seconds max. (at 220C or higher), Count: Three times or less, Exposure limit: 3 daysNote (after that, prebake at 125C for 20 hours)
VPS
Package peak temperature: 215C, Time: 40 seconds max. (at 200C or higher), Count: Three times or less, Exposure limit: 3 daysNote (after that, prebake at 125C for 20 hours)
VP15-203-3
Note
After opening the dry pack, store it at 25C or less and 65%RH or less for the allowable storage period.
Caution Do not use different soldering methods together.
Data Sheet U14042EJ4V0DS
85
PD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
Table 14-2. Insertion Type Soldering Conditions xxx xxx: PD780021ACW-xxx 64-pin plastic SDIP (19.05 mm (750)) xxx: PD780022ACW-xxx 64-pin plastic SDIP (19.05 mm (750)) xxx xxx: PD780023ACW-xxx 64-pin plastic SDIP (19.05 mm (750)) xxx xxx xxx: PD780024ACW-xxx 64-pin plastic SDIP (19.05 mm (750)) xxx: PD780021AYCW-xxx 64-pin plastic SDIP (19.05 mm (750)) xxx xxx: PD780022AYCW-xxx 64-pin plastic SDIP (19.05 mm (750)) xxx xxx: PD780023AYCW-xxx 64-pin plastic SDIP (19.05 mm (750)) xxx xxx: PD780024AYCW-xxx 64-pin plastic SDIP (19.05 mm (750)) xxx
Soldering Method Wave soldering (only for pins) Partial heating Pin temperature: 300C max., Time: 3 seconds max. (per pin row) Soldering Conditions Solder bath temperature: 260C max., Time: 10 seconds max.
Caution Apply wave soldering only to the pins and be careful not to bring solder into direct contact with the package.
86
Data Sheet U14042EJ4V0DS
PD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
APPENDIX A. DEVELOPMENT TOOLS
The following development tools are available for system development using the PD780024A, 780024AY Subseries. Also refer to (6) Cautions on Using Development Tools. (1) Software Package
SP78K0 CD-ROM in which various software tools for 78K/0 development are integrated in one package
(2) Language Processing Software
RA78K0 CC78K0 DF780024 CC78K0-L Assembler package common to 78K/0 Series C compiler package common to 78K/0 Series Device file for PD780024A, 780024AY Subseries C compiler library source file common to 78K/0 Series
(3) Flash Memory Writing Tools
Flashpro III (FL-PR3, PG-FP3) Flashpro IV (FL-PR4, PG-FP4) FA-64CW FA-64GC FA-64GC-8BS-A FA-64GK-9ET FA-64GB-8EU FA-73F1-CN3-A Adapter for flash memory writing used connected to the Flashpro III/Flashpro IV. * FA-64CW: 64-pin plastic SDIP (CW type) * FA-64GC: 64-pin plastic QFP (GC-AB8 type) * FA-64GC-8BS-A: 64-pin plastic LQFP (GC-8BS type) * FA-64GK-9ET: 64-pin plastic TQFP (GK-9ET type) * FA-64GB-8EU: 64-pin plastic LQFP (GB-8EU type) * FA-73F1-CN3-A: 73-pin plastic FBGA (F1-CN3 type) Flash programmer dedicated to microcontrollers with on-chip flash memory
Data Sheet U14042EJ4V0DS
87
PD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
(4) Debugging Tools * When using in-circuit emulator IE-78K0-NS or IE-78K0-NS-A
IE-78K0-NS IE-78K0-NS-PA IE-78K0-NS-A IE-70000-MC-PS-B IE-70000-98-IF-C IE-70000-CD-IF-A IE-70000-PC-IF-C IE-70000-PCI-IF-A IE-780034-NS-EM1 NP-64CW NP-H64CW NP-64GC NP-64GC-TQ NP-H64GC-TQ NP-64GK NP-H64GK-TQ NP-H64GB-TQ NP-73F1-CN3Note EV-9200GC-64 Emulation probe for 64-pin plastic LQFP (GB-8EU type) Emulation probe for 73-pin plastic FBGA (F1-CN3 type) Conversion socket to connect the NP64GC and a target system board on which a 64-pin plastic QFP (GC-AB8 type), 64-pin plastic LQFP (GC-8BS type) can be mounted. Conversion adapter to connect the NP-64GC-TQ or NP-H64GC-TQ and a target system board on which a 64-pin plastic QFP (GC-AB8 type), 64-pin plastic LQFP (GC-8BS type) can be mounted Conversion adapter to connect the NP-64GK or NP-H64GK-TQ and a target system on which a 64pin plastic TQFP (GK-9ET type) can be mounted Conversion socket to connect the NP-H64GB-TQ and a target system board on which a 64-pin plastic LQFP (GB-8EU type) can be mounted CSICE73A0909N01, LSPACK73A0909N01, CSSOCKET73A0909N01 ID78K0-NS SM78K0 DF780024 Integrated debugger for IE-78K0-NS and IE-78K0-NS-A System simulator common to 78K/0 Series Device file for PD780024A, 780024AY Subseries Conversion socket to connect the NP-73F1-CN3 and a target system board on which a 73-pin plastic FBGA (F1-CN3 type) can be mounted Emulation probe for 64-pin plastic TQFP (GK-9ET type) Emulation probe for 64-pin plastic QFP (GC-AB8 type), 64-pin plastic LQFP (GC-8BS type) In-circuit emulator common to 78K/0 Series Performance board to enhance and expand the functions of IE-78K0-NS Combination of IE-78K-NS and IE-78K0-NS-PA Power supply unit for IE-78K0-N and IE-78K0-NS-A Adapter required when using PC-9800 series as host machine (excluding notebook PCs) (C bus supported) PC card and interface cable when using notebook PC as host machine (PCMCIA socket supported) Adapter required when using IBM PC/ATTM or compatible as host machine (ISA bus supported) Adapter required when using PC in which PCI bus is incorporated as host machine Emulation board to emulate PD780024A, 780024AY Subseries Emulation probe for 64-pin plastic SDIP (CW type)
TGC-064SAP
TGK-064SBW
TGB-064SDP
Note
The conversion socket (CSICE73A0909N01, LSPACK73A0909N01, or CSSOCKET73A0909N01) is supplied with the emulation probe (NP-73F1-CN3).
88
Data Sheet U14042EJ4V0DS
PD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
* When using in-circuit emulator IE-78001-R-A
IE-78001-R-A IE-70000-98-IF-C IE-70000-PC-IF-C IE-70000-PCI-IF-A IE-780034-NS-EM1 IE-78K0-R-EX1 EP-78240CW-R EP-78240GC-R EP-78012GK-R EV-9200GC-64 In-circuit emulator common to 78K/0 Series Adapter required when using PC-9800 series as host machine (excluding notebook PCs) (C bus supported) Interface adapter when using IBM PC/AT or compatible as host machine (ISA bus supported) Adapter required when using PC in which PCI bus is incorporated as host machine Emulation board to emulate PD780024A, 780024AY Subseries Emulation probe conversion board necessary when using IE-780034-NS-EM1 on IE-78001-R-A Emulation probe for 64-pin plastic SDIP (CW type) Emulation probe for 64-pin plastic QFP (GC-AB8 type) Emulation probe for 64-pin plastic TQFP (GK-9ET type) Conversion socket to connect the EP-78240GC-R and a target system board on which a 64-pin plastic QFP (GC-AB8 type) can be mounted Conversion adapter to connect the EP-78012GK-R and a target system board on which a 64-pin plastic TQFP (GK-9ET type) can be mounted Integrated debugger for IE-78001-R-A System simulator common to 78K/0 Series Device file for PD780024A, 780024AY Subseries
TGK-064SBW
ID78K0 SM78K0 DF780024
(5) Real-Time OS
RX78K0 Real-time OS for 78K/0 Series
Caution The 64-pin plastic LQFP (GB-8EU type) and 73-pin plastic FBGA (F1-CN3 type) do not support the IE-78001-R-A.
Data Sheet U14042EJ4V0DS
89
PD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
(6) Cautions on Using Development Tools * The ID78K0-NS, ID78K0, and SM78K0 are used in combination with the DF780024. * The CC78K0 and RX78K0 are used in combination with the RA78K0 and the DF780024. * FL-PR3, FL-PR4, FA-64CW, FA-64GC, FA-64GC-8BS-A, FA-64GK-9ET, FA-64GB-8EU, FA-73F1-CN3-A, NP-64CW, NP-H64CW, NP-64GC, NP-64GC-TQ, NP-H64GC-TQ, NP-64GK, NP-H64GK-TQ, NP-H64GB-TQ, and NP-73F1-CN3 are products made by Naito Densei Machida Mfg. Co., Ltd. (+81-45-475-4191). * TGC-064SAP, TGK-064SBW, TGB-064SDP, CSICE73A0909N01, LSPACK73A0909N01, and CSSOCKET73A0909N01 are products made by TOKYO ELETECH CORPORATION. Refer to: Daimaru Kogyo, Ltd. Tokyo Electronic Division (+81-3-3820-7112) Osaka Electronic Division (+81-6-6244-6672) * For third-party development tools, see the Single-chip Microcontroller Development Tool Selection Guide (U11069E). * The host machines and OSs supporting each software are as follows.
Host Machine [OS] Software RA78K0 CC78K0 ID78K0-NS ID78K0 SM78K0 RX78K0
PC PC-9800 series [Japanese WindowsTM] IBM PC/AT and compatibles [Japanese/English Windows] Note
Note
EWS HP9000 series 700TM [HP-UXTM] SPARCstationTM [SunOSTM, SolarisTM] - - -
Note
Note
DOS-based software
90
Data Sheet U14042EJ4V0DS
PD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
APPENDIX B. RELATED DOCUMENTS
The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. Documents Related to Devices
Document Name Document No. U14046E This document
PD780024A, 780034A, 780024AY, 780034AY Subseries User's Manual PD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY Data Sheet PD780021A(A), 780022A(A), 780023A(A), 780024A(A), 780021AY(A), 780022AY(A), 780023AY(A), 780024AY(A) Data Sheet PD78F0034A, 78F0034AY Data Sheet PD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A) Data Sheet
78K/0 Series Instructions User's Manual
U15131E
U14040E To be prepared U12326E
Documents Related to Development Software Tools (User's Manuals)
Document Name RA78K0 Assembler Package Operation Language Structured Assembly Language CC78K0 C Compiler Operation Language SM78K Series System Simulator Ver. 2.30 or Later Operation (Windows Based) External Part User Open Interface Specifications ID78K Series Integrated Debugger Ver. 2.30 or Later RX78K0 Real-time OS Operation (Windows Based) Fundamentals Installation Project Manager Ver. 3.12 or Later (Windows Based) Document No. U14445E U14446E U11789E U14297E U14298E U15373E U15802E U15185E U11537E U11536E U14610E
Documents Related to Development Hardware Tools (User's Manuals)
Document Name IE-78K0-NS In-Circuit Emulator IE-78K0-NS-A In-Circuit Emulator IE-780034-NS-EM1 Emulation Board IE-78001-R-A In-Circuit Emulator IE-78K0-R-EX1 In-Circuit Emulator Document No. U13731E U14889E U14642E U14142E To be prepared
Caution The related documents listed above are subject to change without notice. Be sure to use the latest version of each document for designing.
Data Sheet U14042EJ4V0DS
91
PD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
Documents Related to Flash Memory Writing
Document Name PG-FP3 Flash Memory Programmer User's Manual PG-FP4 Flash Memory Programmer User's Manual Document No. U13502E U15260E
Other Related Documents
Document Name SEMICONDUCTOR SELECTION GUIDE - Products & Packages Semiconductor Device Mounting Technology Manual Quality Grades on NEC Semiconductor Devices NEC Semiconductor Device Reliability/Quality Control System Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD) Document No. X13769E C10535E C11531E C10983E C11892E
Caution The related documents listed above are subject to change without notice. Be sure to use the latest version of each document for designing.
92
Data Sheet U14042EJ4V0DS
PD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
[MEMO]
Data Sheet U14042EJ4V0DS
93
PD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
Note: Purchase of NEC Electronics l 2 C components conveys a license under the Philips I 2C Patent Rights to use these components in an I 2C system, provided that the system conforms to the I 2C Standard Specification as defined by Philips.
FIP and IEBus are trademarks of NEC Electronics Corporation. Windows is either a registered trademark or a trademark of Microsoft Corporation in the United Status and/ or other countries. PC/AT is a trademark of International Business Machines Corporation. HP9000 series 700 and HP-UX are trademarks of Hewlett-Packard Company. SPARCstation is a trademark of SPARC International, Inc. Solaris and SunOS are trademarks of Sun Microsystems, Inc.
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Data Sheet U14042EJ4V0DS
PD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC Electronics product in your application, pIease contact the NEC Electronics office in your country to obtain a list of authorized representatives and distributors. They will verify:
* * * * *
Device availability Ordering information Product release schedule Availability of related technical literature Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) Network requirements
*
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country.
NEC Electronics America, Inc. (U.S.)
Santa Clara, California Tel: 408-588-6000 800-366-9782 Fax: 408-588-6130 800-729-9288
* Filiale Italiana Milano, Italy Tel: 02-66 75 41 Fax: 02-66 75 42 99 * Branch The Netherlands Eindhoven, The Netherlands Tel: 040-244 58 45 Fax: 040-244 45 80 * Tyskland Filial Taeby, Sweden Tel: 08-63 80 820 Fax: 08-63 80 388 * United Kingdom Branch Milton Keynes, UK Tel: 01908-691-133 Fax: 01908-670-290
NEC Electronics Hong Kong Ltd.
Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044
NEC Electronics Hong Kong Ltd.
Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411
NEC Electronics (Europe) GmbH
Duesseldorf, Germany Tel: 0211-65 03 01 Fax: 0211-65 03 327 * Sucursal en Espana Madrid, Spain Tel: 091-504 27 87 Fax: 091-504 28 60 * Succursale Francaise Velizy-Villacoublay, France Tel: 01-30-67 58 00 Fax: 01-30-67 58 99
NEC Electronics Shanghai, Ltd.
Shanghai, P.R. China Tel: 021-6841-1138 Fax: 021-6841-1137
NEC Electronics Taiwan Ltd.
Taipei, Taiwan Tel: 02-2719-2377 Fax: 02-2719-5951
NEC Electronics Singapore Pte. Ltd.
Novena Square, Singapore Tel: 6253-8311 Fax: 6250-3583
J02.11
Data Sheet U14042EJ4V0DS
95
PD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
These commodities, technology or software, must be exported in accordance with the export administration regulations of the exporting country. Diversion contrary to the law of that country is prohibited.
* The information in this document is current as of September, 2002. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. * No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may appear in this document. * NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others. * Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of a customer's equipment shall be done under the full responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. * While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC Electronics products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features. * NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and "Specific". The "Specific" quality grade applies only to NEC Electronics products developed based on a customerdesignated "quality assurance program" for a specific application. The recommended applications of an NEC Electronics product depend on its quality grade, as indicated below. Customers must check the quality grade of each NEC Electronics product before using it in a particular application. "Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots. "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support). "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications not intended by NEC Electronics, they must contact an NEC Electronics sales representative in advance to determine NEC Electronics' willingness to support a given application. (Note) (1) "NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its majority-owned subsidiaries. (2) "NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as defined above).
M8E 02. 11-1

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